SiR158DP
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V)30
RDS(on) (Ω)0.0018 at VGS = 10 V 0.0023 at VGS = 4.5 V
ID (A)a, g60g60g
Qg (Typ.)41.5 nC
FEATURES
•Halogen-free According to IEC 61249-2-21
Definition
•TrenchFET® Gen III Power MOSFET •100 % Rg Tested •100 % UIS Tested
PowerPAK® SO-8APPLICATIONS
6.15 mmS1234D8765DDDSSG5.15 mm •Low-Side Switch for DC/DC Converters
- Servers
D- POL
- VRM •OR-ing
GBottom ViewSOrdering Information: SiR158DP-T1-GE3 (Lead (Pb)-free and Halogen-free)N-Channel MOSFETABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol LimitUnit VDS30Drain-Source Voltage
V
VGS± 20Gate-Source Voltage
TC = 25 °C60gTC = 70 °C60g
IDContinuous Drain Current (TJ = 150 °C)
TA = 25 °C40b, cTA = 70 °C32b, c
A
IDMPulsed Drain Current80
TC = 25 °C60g
ISContinuous Source-Drain Diode Current
TA = 25 °C4.9b, c
IASSingle Pulse Avalanche Current50
L = 0.1 mH
EASmJSingle Pulse Avalanche Energy125
TC = 25 °C83TC = 70 °C53
PDWMaximum Power Dissipation
TA = 25 °C5.4b, cTA = 70 °C3.4b, c
TJ, TstgOperating Junction and Storage Temperature Range - 55 to 150
°C
260Soldering Recommendations (Peak Temperature)d, eTHERMAL RESISTANCE RATINGS
Parameter Symbol TypicalMaximumUnit RthJAt ≤ 10 s1823Maximum Junction-to-Ambientb, f
°C/W
RthJCMaximum Junction-to-Case (Drain)Steady State1.01.5Notes:
a.Based on TC = 25 °C.
b.Surface Mounted on 1\" x 1\" FR4 board.c.t = 10 s.
d.See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is notrequired to ensure adequate bottom side solder interconnection.
e.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.f.Maximum under Steady State conditions is 65 °C/W. g.Package Limited.
Document Number: 64730S09-0318-Rev. A, 02-Mar-09
www.vishay.com
1
http://oneic.com/
New Product
SiR158DP
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Static
Drain-Source Breakdown VoltageVDS Temperature CoefficientVGS(th) Temperature CoefficientGate-Source Threshold VoltageGate-Source Leakage
Zero Gate Voltage Drain CurrentOn-State Drain Currenta
Drain-Source On-State ResistanceaForward TransconductanceaDynamicb
Input CapacitanceOutput Capacitance
Reverse Transfer CapacitanceTotal Gate ChargeGate-Source ChargeGate-Drain ChargeGate ResistanceTurn-On Delay TimeRise Time
Turn-Off Delay TimeFall Time
Turn-On Delay TimeRise Time
Turn-Off Delay TimeFall Time
Drain-Source Body Diode CharacteristicsContinuous Source-Drain Diode CurrentPulse Diode Forward CurrentaBody Diode Voltage
Body Diode Reverse Recovery TimeBody Diode Reverse Recovery ChargeReverse Recovery Fall TimeReverse Recovery Rise Time
ISISMVSDtrrQrrtatb
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C
IS = 4 A
0.7129221514
TC = 25 °C
60801.14533
AVnsnCns
CissCossCrss QgQgs Qgd Rgtd(on) trtd(off) tftd(on) trtd(off) tf
VDD = 10 V, RL = 1 Ω
ID ≅ 10 A, VGEN = 4.5 V, Rg = 1 ΩVDD = 15 V, RL = 1.5 Ω ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω
f = 1 MHz
0.2
VDS = 15 V, VGS = 10 V, ID = 20 A VDS = 15 V, VGS = 4.5 V, ID = 20 A VDS = 15 V, VGS = 0 V, f = 1 MHz
49809154958741.510.613.80.716944928364716
1.43018801850709030
nsΩ
13063
nCpF
VDSΔVDS/TJ ΔVGS(th)/TJ VGS(th) IGSSIDSSID(on) RDS(on) gfs
VGS = 0 V, ID = 250 µA
ID = 250 µA VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 20 A VGS = 4.5 V, ID = 20 A VDS = 10 V, ID = 20 A
30
0.001450.00185100
0.00180.0023
1.230
24- 6.6
2.5± 100110
VmV/°CVnAµAAΩS
Parameter Symbol Test Conditions Min. Typ.Max.Unit Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operationof the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumrating conditions for extended periods may affect device reliability.
www.vishay.com2Document Number: 64730S09-0318-Rev. A, 02-Mar-09
http://oneic.com/
New ProductSiR158DPVishay SiliconixTYPICAL CHARACTERISTICS 25°C, unless otherwise noted80VGS=10Vthru4V64ID- DrainCurrent(A)ID- DrainCurrent(A)VGS=3V488106324TC=25 °C2TC=125 °CTC=- 55 °C23451600.000.51.01.52.02.501VDS-Drain-to-SourceVoltage(V)VGS-Gate-to-SourceVoltage(V)Output Characteristics
0.00306500Transfer Characteristics
CissRDS(on)- On-Resistance(Ω)0.0026C - Capacitance(pF)52000.0022VGS=4.5V39000.0018VGS=10V0.00142600Coss1300Crss0.00100142842567000612182430ID-DrainCurrent(A)VDS-Drain-to-SourceVoltage(V)On-Resistance vs. Drain Current
10ID=20AVGS- Gate-to-SourceVoltage(V)8VDS=10V6VDS=15VRDS(on)- On-Resistance1.8ID=20A1.6Capacitance
VGS=10V1.4(Normalized)VGS=4.5VVDS=20V1.241.020.8001836547290Qg-TotalGateCharge(nC)0.6- 50- 250255075100125150TJ-JunctionTemperature(°C)Gate ChargeDocument Number: 64730S09-0318-Rev. A, 02-Mar-09
On-Resistance vs. Junction Temperature
www.vishay.com
3
http://oneic.com/
New ProductSiR158DPVishay SiliconixTYPICAL CHARACTERISTICS 25°C, unless otherwise noted100TJ=150 °CRDS(on)- On-Resistance(Ω)10IS- SourceCurrent(A)TJ=25 °C0.015ID=20A0.01210.0090.10.0060.010.003TJ=125 °CTJ=25°C0123456789100.0010.00.0000.20.40.60.81.01.2VSD-Source-to-DrainVoltage(V)VGS-Gate-to-SourceVoltage(V)Source-Drain Diode Forward Voltage0.5200On-Resistance vs. Gate-to-Source Voltage0.2VGS(th)Variance(V)160- 0.1ID=5mAPower (W)120- 0.4ID=250 µA80- 0.740- 1.0- 500- 2502550751001251500.0010.010.1Time (s)110TJ-Temperature(°C)Threshold Voltage
100LimitedbyRDS(on)*Single Pulse Power, Junction-to-Ambient10ID-DrainCurrent(A)1ms10ms1100ms1s10s0.1TA=25 °CSinglePulse0.010.01DCBVDSSLimited0.1110100VDS-Drain-to-SourceVoltage(V)*VGS>minimumVGSatwhichRDS(on)isspecifiedSafe Operating Area, Junction-to-Ambient
www.vishay.com4Document Number: 64730S09-0318-Rev. A, 02-Mar-09
http://oneic.com/
New Product
SiR158DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25°C, unless otherwise noted
175140ID-DrainCurrent(A)10570PackageLimited3500255075100125150TC-CaseTemperature(°C)Current Derating*
1002.5802.0Power(W)Power(W)601.5401.0200.5002550751001251500.00255075100125150TC-CaseTemperature(°C)TA-AmbientTemperature(°C)Power, Junction-to-CasePower, Junction-to-Ambient* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upperdissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the packagelimit.
Document Number: 64730S09-0318-Rev. A, 02-Mar-09www.vishay.com
5
http://oneic.com/
New Product
SiR158DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25°C, unless otherwise noted
1DutyCycle=0.5NormalizedEffectiveTransientThermalImpedance0.20.10.05Notes:PDMt10.10.02SinglePulse0.0110-410-310-210-11SquareWavePulseDuration(s)10t21.DutyCycle,D=2.PerUnitBase=RthJA=65 °C/W3.TJM-TA=PDMZthJA(t)4.SurfaceMountedt1t21001000Normalized Thermal Transient Impedance, Junction-to-Ambient
1DutyCycle=0.5NormalizedEffectiveTransientThermalImpedance0.20.10.10.02SinglePulse0.050.0110-410-310-2SquareWavePulseDuration(s)10-11Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see www.vishay.com/ppg?64730.www.vishay.com6Document Number: 64730S09-0318-Rev. A, 02-Mar-09
http://oneic.com/
Package Information
Vishay Siliconix
PowerPAK® SO-8, (SINGLE/DUAL)
HWθM122D1D34L1E3θθE2E4KLD412D2D534bbL1D12K1D534DθA10.150 ± 0.008D2ZecDetail ZD3(2x)D42E1EABackside View of Single PadHKE2E4D2Notes1.Inch will govern.2Dimensions exclusive of mold gate burrs.3.Dimensions exclusive of mold flash and cutting burrs.E3Backside View of Dual PadMILLIMETERS
DIM.AA1bcDD1D2D3D4D5EE1E2E3 E4eKK1HLL1θWM
ECN: T10-0055-Rev. J, 15-Feb-10DWG: 5881
0.560.510.510.060°0.156.055.793.483.68MIN.0.970.000.330.235.054.803.561.32
NOM.1.04-0.410.285.154.903.761.500.57 TYP.3.98 TYP.6.155.893.663.780.75 TYP.1.27 BSC1.27 TYP.
-0.610.610.13-0.250.125 TYP.
-0.710.710.2012°0.36
0.0220.0200.0200.0020°0.006
6.255.993.843.91
0.2380.2280.1370.145
MAX.1.120.050.510.335.265.003.911.68
MIN.0.0380.0000.0130.0090.1990.1890.1400.052
INCHESNOM.0.041-0.0160.0110.2030.1930.1480.0590.0225 TYP.0.157 TYP.0.2420.2320.1440.1490.030 TYP.0.050 BSC0.050 TYP.
-0.0240.0240.005-0.0100.005 TYP.
-0.0280.0280.00812°0.0140.2460.2360.1510.154MAX.0.0440.0020.0200.0130.2070.1970.1540.066
Document Number: 71655Revison: 15-Feb-10
www.vishay.com
1
http://oneic.com/
AN821
Vishay Siliconix
PowerPAK® SO-8 Mounting and Thermal Considerations
Wharton McDaniel
MOSFETs for switching applications are now availablewith die on resistances around 1 mΩ and with thecapability to handle 85 A. While these die capabilitiesrepresent a major advance over what was availablejust a few years ago, it is important for power MOSFETpackaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by thepackage is undesirable. PowerPAK is a new packagetechnology that addresses these issues. In this appli-cation note, PowerPAK’s construction is described.Following this mounting information is presentedincluding land patterns and soldering profiles for max-imum reliability. Finally, thermal and electrical perfor-mance is discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around theSO-8 package (Figure 1). The PowerPAK SO-8 uti-lizes the same footprint and the same pin-outs as thestandard SO-8. This allows PowerPAK to be substi-tuted directly for a standard SO-8 package. Being aleadless package, PowerPAK SO-8 utilizes the entireSO-8 footprint, freeing space normally occupied by theleads, and thus allowing it to hold a larger die than astandard SO-8. In fact, this larger die is slightly largerthan a full sized DPAK die. The bottom of the die attachpad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the deviceis mounted on. Finally, the package height is lowerthan the standard SO-8, making it an excellent choicefor applications with space constraints.
PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pinarrangement (drain, source, gate pins) and the pindimensions are the same as standard SO-8 devices(see Figure 2). Therefore, the PowerPAK connectionpads match directly to those of the SO-8. The only dif-ference is the extended drain connection area. To takeimmediate advantage of the PowerPAK SO-8 singledevices, they can be mounted to existing SO-8 landpatterns.
Standard SO-8PowerPAK SO-8
Figure 2.
The minimum land pattern recommended to take fulladvantage of the PowerPAK thermal performance seeApplication Note 826, Recommended Minimum PadPatterns With Outline Drawing Access for Vishay Sili-conix MOSFETs. Click on the PowerPAK SO-8 singlein the index of this document.
In this figure, the drain land pattern is given to make fullcontact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, andtop of the drawn pattern. This extension will serve toincrease the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to thePC board and therefore to the ambient. Note thatincreasing the drain land area beyond a certain pointwill yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditionsof board configuration, copper weight and layer stack,experiments have found that more than about 0.25 to0.5 in2 of additional copper (in addition to the drainland) will yield little improvement in thermal perfor-mance.
Figure 1. PowerPAK 1212 Devices
Document Number 7162228-Feb-06www.vishay.com
1
http://oneic.com/
AN821
Vishay Siliconix
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and thepin dimensions of the PowerPAK SO-8 dual are thesame as standard SO-8 dual devices. Therefore, thePowerPAK device connection pads match directly tothose of the SO-8. As in the single-channel package,the only exception is the extended drain connectionarea. Manufacturers can likewise take immediateadvantage of the PowerPAK SO-8 dual devices bymounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’sthermal performance, the minimum recommendedland pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With OutlineDrawing Access for Vishay Siliconix MOSFETs. Clickon the PowerPAK 1212-8 dual in the index of this doc-ument.
The gap between the two drain pads is 24 mils. Thismatches the spacing of the two drain pads on the Pow-erPAK SO-8 dual package.
Ramp-Up Rate
Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature Ramp-Down RateFor the lead (Pb)-free solder profile, see http://www.vishay.com/doc?73257.
+ 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C
+ 6 °C/Second Maximum
Time at Maximum Temperature 20 - 40 Seconds
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solderreflow reliability requirements. Devices are subjectedto solder reflow as a test preconditioning and are thenreliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and timeduration, are shown in Figures 3 and 4.
Figure 3. Solder Reflow Temperature Profile
10 s (max)210 - 220 °C3 °C(max)183 °C140 - 170 °C50 s (max)3 °C(max)60 s (min)Pre-Heating ZoneReflow Zone4 ° C/s (max)Maximum peak temperature at 240 °C is allowed.Figure 3. Solder Reflow Temperatures and Time Durations
www.vishay.com
2Document Number 71622
28-Feb-06
http://oneic.com/
AN821
Vishay Siliconix
THERMAL PERFORMANCEIntroduction
A basic measure of a device’s thermal performance isthe junction-to-case thermal resistance, Rθjc, or thejunction-to-foot thermal resistance, Rθjf. This parameteris measured for the device mounted to an infinite heatsink and is therefore a characterization of the deviceonly, in other words, independent of the properties of theobject to which the device is mounted. Table 1 shows acomparison of the DPAK, PowerPAK SO-8, and stan-dard SO-8. The PowerPAK has thermal performanceequivalent to the DPAK, while having an order of magni-tude better thermal performance over the SO-8. TABLE 1.
DPAK and PowerPAK SO-8
Equivalent Steady State Performance
DPAK
Thermal Resistance Rθjc
PowerPAK
SO-81.0 °C/W
StandardSO-816 °C/W
Because of the presence of the trough, this result sug-gests a minimum performance improvement of 10 °C/Wby using a PowerPAK SO-8 in a standard SO-8 PCboard mount.
The only concern when mounting a PowerPAK on astandard SO-8 pad pattern is that there should be notraces running between the body of the MOSFET.Where the standard SO-8 body is spaced away from thepc board, allowing traces to run underneath, the Power-PAK sits directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading cop-per, to the drain pad to aid in conducting heat from adevice. It is helpful to have some information about thethermal performance for a given area of spreading cop-per.
Figure 6 shows the thermal resistance of a PowerPAKSO-8 device mounted on a 2-in. 2-in., four-layer FR-4PC board. The two internal layers and the backside layerare solid copper. The internal layers were chosen assolid copper to model the large power and groundplanes common in many applications. The top layer wascut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken.The results indicate that an area above 0.3 to 0.4 squareinches of spreading copper gives no additional thermalperformance improvement. A subsequent experimentwas run where the copper on the back-side wasreduced, first to 50 % in stripes to mimic circuit traces,and then totally removed. No significant effect wasobserved.
Rth vs. Spreading Copper(0 %, 50 %, 100 % Back Copper)561.2 °C/W
Thermal Performance on Standard SO-8 Pad PatternBecause of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pat-tern. The question then arises as to the thermal perfor-mance of the PowerPAK device under these conditions.A characterization was made comparing a standard SO-8and a PowerPAK device on a board with a trough cut outunderneath the PowerPAK drain pad. This configurationrestricted the heat flow to the SO-8 land pads. Theresults are shown in Figure 5.
Si4874DY vs. Si7446DP PPAK on a 4-Layer BoardSO-8 Pattern, Trough Under Drain6050Impedance (C/watts)40Si4874DY30Si7446DP2010Impedance (C/watts)514641100 %0 %00.00010.011Pulse Duration (sec)1001000050 %360.000.250.500.751.001.251.501.752.00Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal PathFigure 6. Spreading Copper Junction-to-Ambient Performance
www.vishay.com
3
Document Number 7162228-Feb-06
http://oneic.com/
分销商库存信息:
VISHAY
SIR158DP-T1-GE3
因篇幅问题不能全部显示，请点此查看更多更全内容