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DAC5652AIPFB资料

2022-10-20 来源:小奈知识网
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DAC5652Awww.ti.com

SLAS535–SEPTEMBER2007

DUAL,10-BIT275MSPSDIGITAL-TO-ANALOGCONVERTER

FEATURES

10-BitDualTransmitDigital-to-AnalogConverter(DAC)

275MSPSUpdateRate

SingleSupply:3.0Vto3.6V

HighSpurious-FreeDynamicRange(SFDR):80dBcat5MHz

HighThird-OrderTwo-ToneIntermodulation(IMD3):78dBcat15.1MHzand16.1MHzIndependentorSingleResistorGainControlDualorInterleavedDataOn-Chip1.2-VReferenceLowPower:290mW

Power-DownMode:9mW

Package:48-PinThin-QuadFlatPack(TQFP)

APPLICATIONS

CellularBaseTransceiverStationTransmitChannel

–CDMA:W-CDMA,CDMA2000,IS-95–TDMA:GSM,IS-136,EDGE/UWC-136Medical/TestInstrumentation

ArbitraryWaveformGenerators(ARB)DirectDigitalSynthesis(DDS)

CableModemTerminationSystem(CMTS)

•••••••••••

••••

DESCRIPTION

TheDAC5652Aisamonolithic,dual-channel,10-bit,high-speedDACwithon-chipvoltagereference.

Operatingwithupdateratesofupto275MSPS,theDAC5652Aoffersexceptionaldynamicperformance,tight-gain,andoffsetmatchingcharacteristicsthatmakeitsuitableineitherI/QbasebandordirectIFcommunicationapplications.

EachDAChasahigh-impedance,differential-currentoutput,suitableforsingle-endedordifferentialanalog-outputconfigurations.Externalresistorsallowscalingofthefull-scaleoutputcurrentforeachDACseparatelyortogether,typicallybetween2mAand20mA.Anaccurateon-chipvoltagereferenceistemperature-compensatedanddeliversastable1.2-Vreferencevoltage.Optionally,anexternalreferencemaybeused.

TheDAC5652Ahastwo,10-bit,parallelinputportswithseparateclocksanddatalatches.Forflexibility,theDAC5652AalsosupportsmultiplexeddataforeachDACononeportwhenoperatingintheinterleavedmode.TheDAC5652Ahasbeenspecificallydesignedforadifferentialtransformer-coupledoutputwitha50-Ωdoubly-terminatedload.Fora20-mAfull-scaleoutputcurrent,botha4:1impedanceratio(resultinginanoutputpowerof4dBm)and1:1impedanceratiotransformer(–2dBmoutputpower)aresupported.

TheDAC5652Aisavailableina48-pinTQFPpackage.Pincompatibilitybetweenfamilymembersprovides10-bit(DAC5652A),12-bit(DAC5662),and14-bit(DAC5672)resolution.Furthermore,theDAC5652AispincompatibletotheDAC2900andAD9763dualDACs.Thedeviceischaracterizedforoperationovertheindustrialtemperaturerangeof–40°Cto85°C.

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comThesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

FUNCTIONALBLOCKDIAGRAM

WRTBWRTACLKBCLKADE-MUXLatch ADA[9:0]10−b DACIOUTA1IOUTA2BIASJ_ADB[9:0]MODEGSETLatch B10−b DACIOUTB1IOUTB2BIASJ_B1.2 V ReferenceSLEEPEXTIODVDDDGNDAVDDAGNDAVAILABLEOPTIONS

TA

–40°Cto85°C

PACKAGEDDEVICES

48-PinTQFP

DAC5652AIPFBDAC5652AIPFBR

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DEVICEINFORMATION

MODEAVDDIOUTA1IOUTA2BIASJ_AEXTIOGSETBIASJ_BIOUTB2IOUTB1AGNDSLEEPDA9 (MSB)DA8DA7DA6DA5DA4DA3DA2DA1DA0 (LSB)NCNC123456789101148474645444342414039383736353433Top View48-Pin TQFPPFB Package323130292827262512131415161718192021222324NCNCNCNCDB0 (LSB)DB1DB2DB3DB4DB5DB6DB7TERMINAL

NAMEAGNDAVDDBIASJ_ABIASJ_BCLKA/CLKIQCLKB/RESETIQDA[9:0]DB[9:0]DGNDDVDDEXTIOGSETIOUTA1IOUTA2IOUTB1IOUTB2MODENCSLEEPWRTA/WRTIQWRTB/SELECTIQ

NO.3847444118191-1023-3215,2116,224342464539404811-14,33-36

371720

I/OIIOOIIIIIII/OIOOOOI-III

AnaloggroundAnalogsupplyvoltage

Full-scaleoutputcurrentbiasforDACAFull-scaleoutputcurrentbiasforDACB

ClockinputforDACA,CLKIQininterleavedmodeClockinputforDACB,RESETIQininterleavedmodeDataportA.DA9isMSBandDA0isLSB.DataportB.DB9isMSBandDB0isLSB.DigitalgroundDigitalsupplyvoltage

Internalreferenceoutput(bypasswith0.1μFtoAGND)orexternalreferenceinputGain-settingmode:H–1resistor,L–2resistors.Internalpullup.DACAcurrentoutput.Full-scalewithallbitsofDAhigh.

DACAcomplementarycurrentoutput.Full-scalewithallbitsofDAlow.DACBcurrentoutput.Full-scalewithallbitsofDBhigh.

DACBcomplementarycurrentoutput.Full-scalewithallbitsofDBlow.ModeSelect:H–DualBus,L–Interleaved.Internalpullup.

Factoryuseonly.PinsmustbeconnectedtoDGNDorleftunconnected.

Sleepfunctioncontrolinput:H–DACinpower-downmode,L–DACinoperatingmode.Internalpulldown.

InputwritesignalforPORTA(WRTIQininterleavingmode)InputwritesignalforPORTB(SELECTIQininterleavingmode)

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NCNCDGNDDVDDWRTA/WRTIQCLKA/CLKIQCLKB/RESETIQWRTB/SELECTIQDGNDDVDDDB9 (MSB)DB8TERMINALFUNCTIONS

DESCRIPTION

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comABSOLUTEMAXIMUMRATINGS

overTA(unlessotherwisenoted)(1)

UNIT

Supplyvoltagerange

VoltagebetweenAGNDandDGNDVoltagebetweenAVDDandDVDD

DA[9:0]andDB[9:0](3)

Supplyvoltagerange

MODE,CLKA,CLKB,WRTA,WRTBIOUTA1,IOUTA2,IOUTB1,IOUTB2EXTIO,BIASJ_A,BIASJ_B,SLEEP

Peakinputcurrent(anyinput)Peaktotalinputcurrent(allinputs)Operatingfree-airtemperaturerangeStoragetemperaturerange(1)(2)(3)

(3)(2)

AVDD(2)DVDD(3)

–0.5Vto4V–0.5Vto4V–0.5Vto0.5V–4Vto4V–0.5VtoDVDD+0.5V–0.5VtoDVDD+0.5V–1.0VtoAVDD+0.5V–0.5VtoAVDD+0.5V

20mA–30mA–40°Cto85°C–65°Cto150°C

(2)

Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonlyandfunctionaloperationoftheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.MeasuredwithrespecttoAGND.MeasuredwithrespecttoDGND.

ELECTRICALCHARACTERISTICS

overTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA,independentgainsetmode(unlessotherwisenoted)

PARAMETER

DCSpecifications

Resolution

DCAccuracy(1)INLDNL

IntegralnonlinearityDifferentialnonlinearityOffseterrorOffsetmismatchGainerror

Minimumfull-scaleoutputcurrent(2)Maximumfull-scaleoutputcurrent(2)Gainmismatch

Outputvoltagecompliancerange(3)

ROCO

OutputresistanceOutputcapacitanceReferencevoltageReferenceoutputcurrent

ReferenceInputV(EXTIO)RI

InputvoltageInputresistanceSmallsignalbandwidth

(1)(2)(3)(4)4

0.1

1300

1.25

VMΩkHz

(4)

TESTCONDITIONSMIN10–1–0.5

TYPMAXUNITBits

1LSB=I(OUTFS)/210,TMINtoTMAX

±0.25±0.16±0.05±0.03±0.75

220

10.5

LSBLSB%FSR%FSR%FSRmAmA

AnalogOutput

Midscalevalue(internalreference)Midscalevalue(internalreference)Withinternalreference

Withinternalreference–2–1

0.23005

21.25

%FSRVkΩpF

ReferenceOutput

1.14

1.2100

1.26

VnA

Measureddifferentiallythrough50ΩtoAGND.

Nominalfull-scalecurrent,I(OUTFS),equals32xtheI(BIAS)current.

ThelowerlimitoftheoutputcomplianceisdeterminedbytheCMOSprocess.Exceedingthislimitmayresultintransistorbreakdown,resultinginreducedreliabilityoftheDAC5652Adevice.Theupperlimitoftheoutputcomplianceisdeterminedbytheloadresistorsandfull-scaleoutputcurrent.Exceedingtheupperlimitadverselyaffectsdistortionperformanceandintegralnonlinearity.Useanexternalbufferamplifierwithhigh-impedanceinputtodriveanyexternalload.

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ELECTRICALCHARACTERISTICS(continued)

overTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA,independentgainsetmode(unlessotherwisenoted)

PARAMETER

CI

Inputcapacitance

TemperatureCoefficients

Offsetdrift

Withexternalreference

Gaindrift

Withinternalreference

2±20±40±20

ppmofFSR/°CppmofFSR/°CppmofFSR/°Cppm/°C

TESTCONDITIONS

MIN

TYP100

MAX

UNITpF

Referencevoltagedrift

ELECTRICALCHARACTERISTICS

overTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA,fDATA=200MSPS,fOUT=1MHz,independentgainsetmode(unlessotherwisenoted)

PARAMETER

PowerSupplyAVDDDVDD

AnalogsupplyvoltageDigitalsupplyvoltage

Includingoutputcurrentthroughloadresistor

I(AVDD)

Supplycurrent,analog

SleepmodewithclockSleepmodewithoutclock

I(DVDD)

Supplycurrent,digital

SleepmodewithclockSleepmodewithoutclockSleepmodewithclockSleepmodewithoutclockfDATA=275MSPS,fOUT=20MHz

APSRRDPSRRTA

AnalogpowersupplyrejectionratioDigitalpowersupplyrejectionratioOperatingfree-airtemperature

–0.2–0.2–4033

3.33.3752.52.51211.30.6290

Powerdissipation

45.59.2310–0.01

0

0.20.285

%FSR/V%FSR/V°C

360

mW

2018

mA

3.63.690

mAVV

TESTCONDITIONS

MIN

TYP

MAX

UNIT

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comELECTRICALCHARACTERISTICS

ACspecificationsoverTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA,independentgainsetmode,differential1:1impedanceratiotransformercoupledoutput,50-Ωdoublyterminatedload(unlessotherwisenoted)

PARAMETER

AnalogOutputfclktstrtf

Maximumoutputupdaterate(1)

Outputsettlingtimeto0.1%(DAC)

Outputrisetime10%to90%(OUT)

Outputfalltime90%to10%(OUT)Outputnoise

ACLinearity

1stNyquistzone,TA=25°C,

fDATA=50MSPS,fOUT=1MHz,I(OUTFS)=0dB1stNyquistzone,TA=25°C,

fDATA=50MSPS,fOUT=1MHz,I(OUTFS)=–6dB1stNyquistzone,TA=25°C,

fDATA=50MSPS,fOUT=1MHz,I(OUTFS)=–12dB

SFDR

Spurious-freedynamicrange

1stNyquistzone,TA=25°C,

fDATA=100MSPS,fOUT=5MHz,I(OUTFS)=0dB1stNyquistzone,TA=25°C,

fDATA=100MSPS,fOUT=20MHz,I(OUTFS)=0dB1stNyquistzone,TMINtoTMAX,

fDATA=200MSPS,fOUT=20MHz,I(OUTFS)=0dB1stNyquistzone,TA=25°C,

fDATA=200MSPS,fOUT=41MHz,I(OUTFS)=0dB1stNyquistzone,TA=25°C,

fDATA=275MSPS,fOUT=20MHz

SNR

Signal-to-noiseratio

1stNyquistzone,TA=25°C,

fDATA=100MSPS,fOUT=5MHz,I(OUTFS)=0dB1stNyquistzone,TA=25°C,

fDATA=160MSPS,fOUT=20MHz,I(OUTFS)=0dBEachtoneat–6dBFS,TA=25°C,

fDATA=200MSPS,fOUT=45.4MHzand46.4MHzEachtoneat–6dBFS,TA=25°C,

fDATA=100MSPS,fOUT=15.1MHzand16.1MHzEachtoneat–12dBFS,TA=25°C

fDATA=100MSPS,fOUT=15.6,15.8,16.2,and16.4MHz

IMD

Four-toneintermodulation

Eachtoneat–12dBFS,TA=25°C

fDATA=165MSPS,fOUT=19.0,19.1,19.3,and19.4MHz

Eachtoneat–12dBFS,TA=25°C

fDATA=165MSPS,fOUT=68.8,69.6,71.2,and72.0MHz

Channelisolation

(1)

TA=25°C,fDATA=165MSPS

fOUT(CH1)=20MHz,fOUT(CH2)=21MHz

61

79787380

dBc

76706770636261

dBc

7876

dBdB

I(OUTFS)=20mAI(OUTFS)=2mAMid-scaletransition

275

201.41.55530

MSPSnsnsnspA/√Hz

TESTCONDITIONS

MIN

TYP

MAX

UNIT

IMD3

Third-ordertwo-toneintermodulation

55dBc

7090

dBc

Specifiedbydesignandbenchcharacterization.Notproductiontested.

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ELECTRICALCHARACTERISTICS

DigitalspecificationsoverTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA(unlessotherwisenoted)

PARAMETER

DigitalInputVIHVILIIHIILIIH(GSET)IIL(GSET)IIH(MODE)IIL(MODE)CI

High-levelinputvoltageLow-levelinputvoltageHigh-levelinputcurrentLow-levelinputcurrent

High-levelinputcurrent,GSETpinLow-levelinputcurrent,GSETpinHigh-levelinputcurrent,MODEpinLow-levelinputcurrent,MODEpinInputcapacitance

20

±50±107–80–30–805

3.30.8

VVAAAAAApF

TESTCONDITIONS

MIN

TYP

MAX

UNIT

SWITCHINGCHARACTERISTICS

DigitalspecificationsoverTA,AVDD=DVDD=3.3V,I(OUTFS)=20mA(unlessotherwisenoted)

PARAMETER

Timing-DualBusModetsuthtLPHtLATtPDtsuthtLATtPD

InputsetuptimeInputholdtime

InputclockpulsehightimeClocklatency(WRTA/Btooutputs)PropagationdelaytimeInputsetuptimeInputholdtime

Clocklatency(WRTA/Btooutputs)Propagationdelaytime

4

1.5

4

1.50.50.5

4

11

1

4

nsnsnsclknsnsnsclkns

TESTCONDITIONS

MIN

TYP

MAX

UNIT

Timing-SingleBusInterleavedMode

TYPICALCHARACTERISTICS

INTEGRALNONLINEARITY

vs

INPUTCODE

INL − Integral Nonlinearity Error − LSB0.50.40.30.20.10.0−0.1−0.2−0.3−0.4−0.50100200300400500Input Code6007008009001000G001Figure1.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comTYPICALCHARACTERISTICS(continued)

DIFFERENTIALNONLINEARITY

vs

INPUTCODE

DNL − Differential Nonlinearity Error − LSB0.250.200.150.100.050.00−0.05−0.10−0.15−0.20−0.25

0

100

200

300

400

500Input Code

600

700

800

900

1000

G002

Figure2.

SPURIOUS-FREEDYNAMICRANGE

vs

OUTPUTFREQUENCY

SPURIOUS-FREEDYNAMICRANGE

vs

OUTPUTFREQUENCY

100SFDR − Spurious-Free Dynamic Range − dBc100SFDR − Spurious-Free Dynamic Range − dBc9590858075fdata = 52 MSPSDual Bus Mode9590858075fdata = 78 MSPSDual Bus Mode−6 dBfS0 dBfS−6 dBfS−12 dBfS706560048121620G003−12 dBfS706560051015202530G0040 dBfSfout − Output Frequency − MHzFigure3.

fout − Output Frequency − MHzFigure4.

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TYPICALCHARACTERISTICS(continued)

SPURIOUS-FREEDYNAMICRANGE

vs

OUTPUTFREQUENCY

SPURIOUS-FREEDYNAMICRANGE

vs

OUTPUTFREQUENCY

100SFDR − Spurious-Free Dynamic Range − dBc100SFDR − Spurious-Free Dynamic Range − dBc95908580757065600fdata = 100 MSPSDual Bus Mode95908580fdata = 165 MSPSDual Bus Mode−6 dBfS0 dBfS0 dBfS7570−12 dBfS6560−6 dBfS−12 dBfS5101520253035G005051015202530354045505560fout − Output Frequency − MHzFigure6.

SINGLE-TONESPECTRUMG006fout − Output Frequency − MHzFigure5.

SINGLE-TONESPECTRUM0fdata = 78 MSPSfOUT = 15 MHzDual Bus Mode0fdata = 165 MSPSfOUT = 30.1 MHzDual Bus Mode−20−20Power − dBm−40Power − dBm−40−60−60−80−80−1000.07.815.623.431.239.0G007−1000.016.533.049.566.082.5G008f − Frequency − MHzFigure7.

f − Frequency − MHzFigure8.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comTYPICALCHARACTERISTICS(continued)

TWO-TONEIMD3

vs

OUTPUTFREQUENCY

TWO-TONEIMD3

vs

OUTPUTFREQUENCY

95908580757065600fdata = 78 MSPSDual Bus Modefout2 = fout1 + 1 MHz5101520253035G0091009590Two-Tone IMD3 − dBcTwo-Tone IMD3 − dBc85807570656055500fdata = 165 MSPSDual Bus Modefout2 = fout1 + 1 MHz1020304050G010fout1 − Output Frequency − MHzFigure9.

TWO-TONESPECTRUM

−10fdata = 78 MSPSfout1 = 20.1 MHzfout2 = 21.1 MHzDual Bus Modefout1 − Output Frequency − MHzFigure10.

TWO-TONESPECTRUM

−10fout1 = 30.1 MHzfout2 = 31.1 MHzDual Bus Modefdata = 165 MSPS−30−30Power − dBmPower − dBm−50−50−70−70−90−90−11019.019.520.020.521.021.522.0G011−11029.029.530.030.531.031.532.0G012f − Frequency − MHzf − Frequency − MHzFigure11.Figure12.

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DigitalInputsandTiming

DigitalInputs

ThedatainputportsoftheDAC5652AacceptastandardpositivecodingwithdatabitsDA9andDB9beingthemostsignificantbits(MSB).Theconverteroutputssupportaclockrateofupto275MSPS.Thebestperformanceistypicallyachievedwithasymmetricdutycycleforwriteandclock;however,thedutycyclemayvaryaslongasthetimingspecificationsaremet.Similarly,thesetupandholdtimesmaybechosenwithintheirspecifiedlimits.

AlldigitalinputsoftheDAC5652AareCMOScompatible.Figure13andFigure14showschematicsoftheequivalentCMOSdigitalinputsoftheDAC5652A.The10-bitdigitaldatainputfollowstheoffsetpositivebinarycodingscheme.TheDAC5652Aisdesignedtooperatewithadigitalsupply(DVDD)of3Vto3.6V.

DVDDDA[9:0]DB[9:0]SLEEPCLKA/BWRTA/BInternalDigital InDGNDFigure13.CMOS/TTLDigitalEquivalentInputWithInternalPulldownResistor

DVDDGSETMODEInternalDigital InDGNDFigure14.CMOS/TTLDigitalEquivalentInputWithInternalPullupResistor

InputInterfaces

TheDAC5652AfeaturestwooperatingmodesselectedbytheMODEpin,asshowninTable1.•Fordual-businputmode,thedeviceessentiallyconsistsoftwoseparateDACs.EachDAChasitsownseparatedatainputbus,clockinput,anddatawritesignal(datalatch-in).

•Insingle-businterleavedmode,thedatamustbepresentedinterleavedattheA-channelinputbus.TheB-channelinputbusisnotusedinthismode.TheclockandwriteinputarenowsharedbybothDACs.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comTable1.OperatingModes

MODEPinBusinput

MODEpinconnectedtoDGND

Single-businterleavedmode,clockandwriteinputequalforbothDACs

MODEpinconnectedtoDVDD

Dual-busmode,DACsoperateindependently

Dual-BusDataInterfaceandTiming

Indual-busmode,theMODEpinisconnectedtoDVDD.ThetwoconverterchannelswithintheDAC5652Aconsistoftwoindependent,10-bit,paralleldataports.EachDACchanneliscontrolledbyitsownsetofwrite(WRTA,WRTB)andclock(CLKA,CLKB)lines.TheWRTA/BlinescontrolthechannelinputlatchesandtheCLKA/BlinescontroltheDAClatches.ThedataisfirstloadedintotheinputlatchbyarisingedgeoftheWRTA/Bline.

Theinternaldatatransferrequiresacorrectsequenceofwriteandclockinputs,sinceessentiallytwoclockdomainshavingequalperiods(butpossiblydifferentphases)areinputtotheDAC5652A.Thisisdefinedbyaminimumrequirementofthetimebetweentherisingedgeoftheclockandtherisingedgeofthewriteinputs.ThisessentiallyimpliesthattherisingedgeofCLKA/BmustoccuratthesametimeorbeforetherisingedgeoftheWRTA/Bsignal.Aminimumdelayof2nsmustbemaintainediftherisingedgeoftheclockoccursaftertherisingedgeofthewrite.Notethattheseconditionsaresatisfiedwhentheclockandwriteinputsareconnectedexternally.NotethatallspecificationsweremeasuredwiththeWRTA/BandCLKA/Blinesconnectedtogether.

DA[9:0]/DB[9:0]Valid DatatsutLPHthWRTA/WRTBCLKA/CLKBtstPDtLATIOUTorIOUTFigure15.Dual-BusModeOperation

Single-BusInterleavedDataInterfaceandTiming

Insingle-businterleavedmode,theMODEpinisconnectedtoDGND.Figure16showsthetimingdiagram.Ininterleavedmode,theA-andB-channelssharethewriteinput(WRTIQ)andupdateclock(CLKIQandinternalCLKDACIQ).MultiplexinglogicdirectstheinputwordattheA-channelinputbustoeithertheA-channelinputlatch(SELECTIQishigh)ortotheB-channelinputlatch(SELECTIQislow).WhenSELECTIQishigh,thedatavalueintheB-channellatchisretainedbypresentingthelatchoutputdatatoitsinputagain.WhenSELECTIQislow,thedatavalueintheA-channellatchisretainedbypresentingthelatchoutputdatatoitsinput.

Ininterleavedmode,theA-channelinputdatarateistwicetheupdaterateoftheDACcore.Asindual-busmode,itisimportanttomaintainacorrectsequenceofwriteandclockinputs.Theedge-triggeredflip-flopslatchtheA-andB-channelinputwordsontherisingedgeofthewriteinput(WRTIQ).ThisdataispresentedtotheA-andB-DAClatchesonthefollowingfallingedgeofthewriteinputs.TheDAC5652AclockinputisdividedbyafactoroftwobeforeitispresentedtotheDAClatches.

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CorrectpairingoftheA-andB-channeldataisdonebyRESETIQ.Ininterleavedmode,theclockinputCLKIQisdividedbytwo,whichwouldtranslatetoanon-deterministicrelationbetweentherisingedgesoftheCLKIQandCLKDACIQ.RESETIQensures,however,thatthecorrectpositionoftherisingedgeofCLKDACIQwithrespecttothedataattheinputoftheDAClatchisdetermined.CLKDACIQisdisabled(low)whenRESETIQishigh.

DA[9:0]Valid DatatsuSELECTIQthWRTIQCLKIQRESETIQtstPDtLATIOUTorIOUTFigure16.Single-BusInterleavedModeOperation

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comAPPLICATIONINFORMATION

TheoryofOperation

ThearchitectureoftheDAC5652Ausesacurrentsteeringtechniquetoenablefastswitchingandhighupdaterate.ThecoreelementwithinthemonolithicDACisanarrayofsegmentedcurrentsourcesthataredesignedtodeliverafull-scaleoutputcurrentofupto20mA.AninternaldecoderaddressesthedifferentialcurrentswitcheseachtimetheDACisupdatedandacorrespondingoutputcurrentisformedbysteeringallcurrentstoeitheroutputsummingnode,IOUT1orIOUT2.Thecomplementaryoutputsdeliveradifferentialoutputsignal,whichimprovesthedynamicperformancethroughreductionofeven-orderharmonics,common-modesignals(noise),anddoublethepeak-to-peakoutputsignalswingbyafactoroftwo,ascomparedtosingle-endedoperation.Thesegmentedarchitectureresultsinasignificantreductionoftheglitchenergyandimprovesthedynamicperformance(SFDR)andDNL.Thecurrentoutputsmaintainaveryhighoutputimpedanceofgreaterthan300kΩ.

Whenpin42(GSET)ishigh(simultaneousgainsetmode),thefull-scaleoutputcurrentforbothDACsisdeterminedbytheratiooftheinternalreferencevoltage(1.2V)andanexternalresistor(RSET)connectedtoBIASJ_A.WhenGSETislow(independentgainsetmode),thefull-scaleoutputcurrentforeachDACisdeterminedbytheratiooftheinternalreferencevoltage(1.2V)andseparateexternalresistors(RSET)connectedtoBIASJ_AandBIASJ_B.TheresultingIREFisinternallymultipliedbyafactorof32toproduceaneffectiveDACoutputcurrentthatcanrangefrom2mAto20mA,dependingonthevalueofRSET.

TheDAC5652Aissplitintoadigitalandananalogportion,eachofwhichispoweredthroughitsownsupplypin.Thedigitalsectionincludesedge-triggeredinputlatchesandthedecoderlogic,whiletheanalogsectioncomprisesboththecurrentsourcearraywithitsassociatedswitches,andthereferencecircuitry.

DACTransferFunction

EachoftheDACsintheDAC5652Ahasasetofcomplementarycurrentoutputs,IOUT1andIOUT2.Thefull-scaleoutputcurrent,IOUTFS,isthesummationofthetwocomplementaryoutputcurrents:

I+I)IOUTFSOUT1OUT2(1)TheindividualoutputcurrentsdependontheDACcodeandcanbeexpressedas:

IǒǓI+I ǒ1023*CodeǓOUT2OUTFS1024OUT1+I CodeOUTFS1024(2)(3)

whereCodeisthedecimalrepresentationoftheDACdatainputword.Additionally,IOUTFSisafunctionofthe

referencecurrentIREF,whichisdeterminedbythereferencevoltageandtheexternalsettingresistor(RSET).

VI+32 I+32 REFOUTFSREFRSET(4)Inmostcases,thecomplementaryoutputsdriveresistiveloadsoraterminatedtransformer.Asignalvoltage

developsateachoutputaccordingto:

V+I ROUT1OUT1LOAD(5)V+I ROUT2OUT2LOAD(6)ThevalueoftheloadresistanceislimitedbytheoutputcompliancespecificationoftheDAC5652A.Tomaintain

specifiedlinearityperformance,thevoltageforIOUT1andIOUT2mustnotexceedthemaximumallowablecompliancerange.

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Thetotaldifferentialoutputvoltageis:

V+V*VOUTDIFFOUT1OUT2(2 Code*1023)V+ I ROUTDIFFOUTFSLOAD1024AnalogOutputs

(7)(8)

TheDAC5652Aprovidestwocomplementarycurrentoutputs,IOUT1andIOUT2.Thesimplifiedcircuitofthe

analogoutputstagerepresentingthedifferentialtopologyisshowninFigure17.TheoutputimpedanceofIOUT1andIOUT2resultsfromtheparallelcombinationofthedifferentialswitches,alongwiththecurrentsourcesandassociatedparasiticcapacitances.

AVDDS(1)S(1)CS(2)S(2)CS(N)S(N)CIOUT1IOUT2Current Source ArrayRLOADRLOADFigure17.AnalogOutputs

Thesignalvoltageswingthatmaydevelopatthetwooutputs,IOUT1andIOUT2,islimitedbyanegativeandpositivecompliance.Thenegativelimitof–1VisgivenbythebreakdownvoltageoftheCMOSprocessandexceedingitcompromisesthereliabilityoftheDAC5652A(orevencausespermanentdamage).Withthefull-scaleoutputsetto20mA,thepositivecomplianceequals1.2V.Notethatthecompliancerangedecreasestoabout1VforaselectedoutputcurrentofI(OUTFS)=2mA.CaremustbetakenthattheconfigurationofDAC5652Adoesnotexceedthecompliancerangetoavoiddegradationofthedistortionperformanceandintegrallinearity.

Bestdistortionperformanceistypicallyachievedwiththemaximumfull-scaleoutputsignallimitedtoapproximately0.5VPP.Thisisthecasefora50-Ωdoubly-terminatedloadanda20-mAfull-scaleoutputcurrent.AvarietyofloadscanbeadaptedtotheoutputoftheDAC5652AbyselectingasuitabletransformerwhilemaintainingoptimumvoltagelevelsatIOUT1andIOUT2.Furthermore,usingthedifferentialoutputconfigurationincombinationwithatransformerisinstrumentalforachievingexcellentdistortionperformance.Common-modeerrors,suchaseven-orderharmonicsornoise,canbesubstantiallyreduced.Thisisparticularlythecasewithhighoutputfrequencies.

Forthoseapplicationsrequiringtheoptimumdistortionandnoiseperformance,itisrecommendedtoselectafull-scaleoutputof20mA.Alowerfull-scalerangeof2mAmaybeconsideredforapplicationsthatrequirelowpowerconsumption,butcantolerateaslightreductioninperformancelevel.

OutputConfigurations

ThecurrentoutputsoftheDAC5652Aallowforavarietyofconfigurations.Asmentionedpreviously,utilizingtheconverter’sdifferentialoutputsyieldthebestdynamicperformance.SuchadifferentialoutputcircuitmayconsistofanRFtransformeroradifferentialamplifierconfiguration.Thetransformerconfigurationisidealformostapplicationswithaccoupling,whileopampsaresuitableforadc-coupledconfiguration.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comThesingle-endedconfigurationmaybeconsideredforapplicationsrequiringaunipolaroutputvoltage.Connectingaresistorfromeitheroneoftheoutputstogroundconvertstheoutputcurrentintoaground-referencedvoltagesignal.Toimproveonthedclinearitybymaintainingavirtualground,anI-to-Vorop-ampconfigurationmaybeconsidered.

DifferentialWithTransformer

UsinganRFtransformerprovidesaconvenientwayofconvertingthedifferentialoutputsignalintoasingle-endedsignalwhileachievingexcellentdynamicperformance.Theappropriatetransformermustbecarefullyselectedbasedontheoutputfrequencyspectrumandimpedancerequirements.

Thedifferentialtransformerconfigurationhasthebenefitofsignificantlyreducingcommon-modesignals,thusimprovingthedynamicperformanceoverawiderangeoffrequencies.Furthermore,byselectingasuitableimpedanceratio(windingratio)thetransformercanprovideoptimumimpedancematchingwhilecontrollingthecompliancevoltagefortheconverteroutputs.

Figure18andFigure19show50-Ωdoubly-terminatedtransformerconfigurationswith1:1and4:1impedanceratios,respectively.Notethatthecentertapoftheprimaryinputofthetransformerhastobegroundedtoenableadc-currentflow.Applyinga20-mAfull-scaleoutputcurrentwouldleadtoa0.5-VPPoutputfora1:1transformeranda1-VPPoutputfora4:1transformer.Ingeneral,the1:1transformerconfigurationhasabetteroutputdistortion,butthe4:1transformerhas6dBhigheroutputpower.

50 ΩIOUT1100 ΩIOUT250 ΩAGND1:1RLOAD50 ΩFigure18.DrivingaDoubly-Terminated50-ΩCableUsinga1:1ImpedanceRatioTransformer

100 ΩIOUT1AGNDIOUT2100 Ω4:1RLOAD50 ΩFigure19.DrivingaDoubly-Terminated50-ΩCableUsinga4:1ImpedanceRatioTransformer

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Single-EndedConfiguration

Figure20showsthesingle-endedoutputconfiguration,wheretheoutputcurrentIOUT1flowsintoanequivalentloadresistanceof25Ω.NodeIOUT2mustbeconnectedtoAGNDorterminatedwitharesistorof25ΩtoAGND.Thenominalresistorloadof25Ωgivesadifferentialoutputswingof1VPPwhenapplyinga20-mAfull-scaleoutputcurrent.

IOUT1RLOAD50 ΩIOUT250 ΩAGND25 ΩFigure20.DrivingaDoubly-Terminated50-ΩCableUsingaSingle-EndedOutput

ReferenceOperation

InternalReference

TheDAC5652Ahasanon-chipreferencecircuitwhichcomprisesa1.2-Vbandgapreferenceandtwocontrolamplifiers,oneforeachDAC.Thefull-scaleoutputcurrent,I(OUTFS),oftheDAC5652Aisdeterminedbythereferencevoltage,VREF,andthevalueofresistorRSET.I(OUTFS)iscalculatedby:

VI+32 I+32 REFOUTFSREFRSET(9)ThereferencecontrolamplifieroperatesasaV-to-Iconverterproducingareferencecurrent,IREF,whichis

determinedbytheratioofVREFandRSET(seeEquation9).Thefull-scaleoutputcurrent,I(OUTFS),resultsfrommultiplyingIREFbyafixedfactorof32.

Usingtheinternalreference,a2-kΩresistorvalueresultsinafull-scaleoutputofapproximately20mA.Resistorswithatoleranceof1%orbettershouldbeconsidered.Selectinghighervalues,theoutputcurrentcanbeadjustedfrom20mAdownto2mA.OperatingtheDAC5652Aatlowerthan20-mAoutputcurrentsmaybedesirableforreasonsofreducingthetotalpowerconsumption,improvingthedistortionperformance,orobservingtheoutputcompliancevoltagelimitationsforagivenloadcondition.

ItisrecommendedtobypasstheEXTIOpinwithaceramicchipcapacitorof0.1Formore.Thecontrolamplifierisinternallycompensatedanditssmallsignalbandwidthisapproximately300kHz.ExternalReference

TheinternalreferencecanbedisabledbysimplyapplyinganexternalreferencevoltageintotheEXTIOpin,whichinthiscasefunctionsasaninput.Theuseofanexternalreferencemaybeconsideredforapplicationsthatrequirehigheraccuracyanddriftperformanceortoaddtheabilityofdynamicgaincontrol.

Whilea0.1-µFcapacitorisrecommendedtobeusedwiththeinternalreference,itisoptionalfortheexternalreferenceoperation.Thereferenceinput,EXTIO,hasahighinputimpedance(1MΩ)andcaneasilybedrivenbyvarioussources.Notethatthevoltagerangeoftheexternalreferencemuststaywithinthecompliancerangeofthereferenceinput.

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DAC5652ASLAS535–SEPTEMBER2007

www.ti.comGainSettingOption

Thefull-scaleoutputcurrentontheDAC5652Acanbesettwoways:eitherforeachofthetwoDACchannelsindependentlyorforbothchannelssimultaneously.Fortheindependentgainsetmode,theGSETpin(pin42)mustbelow(thatis,connectedtoAGND).Inthismode,twoexternalresistorsarerequired—oneRSETconnectedtotheBIASJ_Apin(pin44)andtheothertotheBIASJ_Bpin(pin41).Inthisconfiguration,theuserhastheflexibilitytosetandadjustthefull-scaleoutputcurrentforeachDACindependently,allowingforthecompensationofpossiblegainmismatcheselsewherewithinthetransmitsignalpath.

Alternatively,bringingtheGSETpinhigh(thatis,connectedtoAVDD),theDAC5652Aswitchesintothesimultaneousgainsetmode.Nowthefull-scaleoutputcurrentofbothDACchannelsisdeterminedbyonlyoneexternalRSETresistorconnectedtotheBIASJ_Apin.TheresistorattheBIASJ_Bpinmayberemoved;however,thisisnotrequiredsincethispinisnotfunctionalinthismodeandtheresistorhasnoeffectonthegainequation.

SleepMode

TheDAC5652Afeaturesapower-downfunctionwhichcanreducethetotalsupplycurrenttoapproximately3.1mAoverthespecifiedsupplyrangeifnoclockispresent.ApplyingalogichightotheSLEEPpininitiatesthepower-downmode,whilealogiclowenablesnormaloperation.Whenleftunconnected,aninternalactivepulldowncircuitenablesthenormaloperationoftheconverter.

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PACKAGEOPTIONADDENDUM

www.ti.com

5-Oct-2007

PACKAGINGINFORMATION

OrderableDeviceDAC5652AIPFBDAC5652AIPFBG4DAC5652AIPFBRDAC5652AIPFBRG4

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVE

PackageTypeTQFPTQFPTQFPTQFP

PackageDrawingPFBPFBPFBPFB

PinsPackageEcoPlan(2)

Qty48484848

250250

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEARLevel-2-260C-1YEAR

1000Green(RoHS&

noSb/Br)1000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

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PACKAGEMATERIALSINFORMATION

www.ti.com

11-Mar-2008

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingTQFP

PFB

48

SPQ

ReelReelDiameterWidth(mm)W1(mm)330.0

16.4

A0(mm)B0(mm)K0(mm)

P1(mm)12.0

WPin1(mm)Quadrant16.0

Q2

DAC5652AIPFBR10009.69.61.5

PackMaterials-Page1

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PACKAGEMATERIALSINFORMATION

www.ti.com

11-Mar-2008

*Alldimensionsarenominal

DeviceDAC5652AIPFBR

PackageType

TQFP

PackageDrawing

PFB

Pins48

SPQ1000

Length(mm)

346.0

Width(mm)346.0

Height(mm)

33.0

PackMaterials-Page2

元器件交易网www.cecb2b.com MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK0,5036250,270,170,08M372448130,13 NOM15,50 TYP7,20SQ6,809,20SQ8,800,05 MIN1,050,95Seating Plane0,750,45Gage Plane0,250°–7°121,20 MAX0,084073176/B 10/96NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Falls within JEDEC MS-026POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com

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