一、实验目的:
1.学会熟练使用quartus8.1编译工具。 2.熟悉VHDL设计方法。 3.熟悉时序电路分析。
二、实验内容:
用16*16点阵做一个循环彩灯,让彩灯从上到下亮一行,灭一行,以此类推。 三、实验条件:
1.电脑。
2.开发软件:QuartusII 8.1。
3.实验设备:EP1K100QC208-3EDA实验箱。 4.连接线若干。
四、实验设计:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; -----------
ENTITY CDCZQ IS
PORT(CLK,DISCLK,K:IN STD_LOGIC;
SEL:OUT STD_LOGIC_vector(3 DOWNTO 0 ); L:OUT STD_LOGIC_vector(15 DOWNTO 0 ) );
END CDCZQ;
ARCHITECTURE behave OF CDCZQ is
signal Q:STD_LOGIC_vector(3 DOWNTO 0 ); signal DIV:STD_LOGIC_vector(3 DOWNTO 0 ); signal AL:STD_LOGIC_vector(3 DOWNTO 0 ); signal AH:STD_LOGIC_vector(1 DOWNTO 0 ); signal DIVCLK:STD_LOGIC; signal CLK_OUT: STD_LOGIC; signal CO:STD_LOGIC; BEGIN
---------------------------16
a1:process(disclk) begin
if disclk'event and disclk='1' then if Q=\"1111\" THEN Q<=\"0000\"; ELSE
Q<=Q+\"0001\"; END IF; END IF; SEL<=Q;
END PROCESS; a2:process(clk) begin
if clk'event and clk='1' then if DIV=\"1111\" THEN
DIV<=\"0000\";DIVCLK<='0'; ELSE
DIV<=DIV+\"0001\";DIVCLK<='1'; END IF; END IF; END PROCESS;
CLK_OUT<=CLK WHEN K='0' ELSE DIVCLK; a3:process(clk_out) begin
if clk_out'event and clk_out='1' then if AL=\"1111\" THEN
AL<=\"0000\";CO<='0'; ELSE
AL<=AL+\"0001\";CO<='1'; END IF; END IF;
END PROCESS; ---------------- a4:process(co) begin
if co'event and co='1' then if AH=\"11\" THEN AH<=\"00\"; ELSE
AH<=AH+'1'; END IF; END IF;
END PROCESS;
a5:PROCESS(AL,AH)
BEGIN
CASE AH IS WHEN \"00\"=> CASE AL IS
WHEN \"0000\"=>L<=\"0000000000000001\"; WHEN \"0001\"=>L<=\"0000000000000011\"; WHEN \"0010\"=>L<=\"0000000000000111\"; WHEN \"0011\"=>L<=\"0000000000001111\"; WHEN \"0100\"=>L<=\"0000000000011111\"; WHEN \"0101\"=>L<=\"0000000000111111\"; WHEN \"0110\"=>L<=\"0000000001111111\"; WHEN \"0111\"=>L<=\"0000000011111111\"; WHEN \"1000\"=>L<=\"0000000111111111\"; WHEN \"1001\"=>L<=\"0000001111111111\"; WHEN \"1010\"=>L<=\"0000011111111111\"; WHEN \"1011\"=>L<=\"0000111111111111\"; WHEN \"1100\"=>L<=\"0001111111111111\"; WHEN \"1101\"=>L<=\"0011111111111111\"; WHEN \"1110\"=>L<=\"0111111111111111\"; WHEN \"1111\"=>L<=\"1111111111111111\"; WHEN others=>l<=\"1111111111111111\"; end case;
WHEN \"01\"=> CASE AL IS
WHEN \"0000\"=>L<=\"0111111111111111\"; WHEN \"0001\"=>L<=\"0011111111111111\"; WHEN \"0010\"=>L<=\"0001111111111111\"; WHEN \"0011\"=>L<=\"0000111111111111\"; WHEN \"0100\"=>L<=\"0000011111111111\"; WHEN \"0101\"=>L<=\"0000001111111111\"; WHEN \"0110\"=>L<=\"0000000111111111\"; WHEN \"0111\"=>L<=\"0000000011111111\"; WHEN \"1000\"=>L<=\"0000000001111111\"; WHEN \"1001\"=>L<=\"0000000000111111\"; WHEN \"1010\"=>L<=\"0000000000011111\"; WHEN \"1011\"=>L<=\"0000000000001111\"; WHEN \"1100\"=>L<=\"0000000000000111\"; WHEN \"1101\"=>L<=\"0000000000000011\"; WHEN \"1110\"=>L<=\"0000000000000001\"; WHEN \"1111\"=>L<=\"0000000000000000\"; WHEN others=>l<=\"0000000000000000\"; end case;
WHEN \"10\"=> CASE AL IS
WHEN \"0000\"=>L<=\"0000000110000000\"; WHEN \"0001\"=>L<=\"0000001111000000\"; WHEN \"0010\"=>L<=\"0000011111100000\"; WHEN \"0011\"=>L<=\"0000111111110000\"; WHEN \"0100\"=>L<=\"0001111111111000\"; WHEN \"0101\"=>L<=\"0011111111111100\"; WHEN \"0110\"=>L<=\"0111111111111110\"; WHEN \"0111\"=>L<=\"1111111111111111\"; WHEN \"1000\"=>L<=\"1111111001111111\"; WHEN \"1001\"=>L<=\"1111110000111111\"; WHEN \"1010\"=>L<=\"1111100000011111\"; WHEN \"1011\"=>L<=\"1111000000001111\"; WHEN \"1100\"=>L<=\"1110000000000111\"; WHEN \"1101\"=>L<=\"1100000000000011\"; WHEN \"1110\"=>L<=\"1000000000000001\"; WHEN \"1111\"=>L<=\"0000000000000000\"; WHEN others=>l<=\"0000000000000000\"; end case;
WHEN \"11\"=> CASE AL IS
WHEN \"0000\"=>L<=\"0000000000000001\"; WHEN \"0001\"=>L<=\"0000000000000000\"; WHEN \"0010\"=>L<=\"0000000000000011\"; WHEN \"0011\"=>L<=\"0000000000000000\"; WHEN \"0100\"=>L<=\"0000000000000111\"; WHEN \"0101\"=>L<=\"0000000000000000\"; WHEN \"0110\"=>L<=\"0000000000001111\"; WHEN \"0111\"=>L<=\"0000000000000000\"; WHEN \"1000\"=>L<=\"0000000000011111\"; WHEN \"1001\"=>L<=\"0000000000000000\"; WHEN \"1010\"=>L<=\"0000000000111111\"; WHEN \"1011\"=>L<=\"0000000000000000\"; WHEN \"1100\"=>L<=\"0000000001111111\"; WHEN \"1101\"=>L<=\"0000000000000000\"; WHEN \"1110\"=>L<=\"0000000011111111\"; WHEN \"1111\"=>L<=\"0000000000000000\"; WHEN others=>l<=\"0000000000000000\"; END CASE; END CASE; END PROCESS; END behave ;
仿真波形如下:
实验总结
通过这次的课程设计,我学到了许多东西,了解到循环彩灯是怎么实现的,通过这次编程,我掌握了对VHDL的基础,再以后的学习中打下更牢,更好的编程风格!
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