TECHNICAL DATA
OCTAL BUFFER/LINE DRIVE; 3-STATE
KK74LV240
The KK74LV240 is a low-voltage Si-gate CMOS device and is pin and function compatible with KK74HC/HCT240.
The KK74LV240 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state.
The KK74LV240 is identical to the KK74LV244 but has inverting 20outputs.
N SUFFIX PLASTIC DIP1201 • • • • • Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 3.6 V
Low Input Current: 1.0 µA, 0.1 µА at Т = 25 °С Output Current: 8 mA at VCC = 3.0 V
High Noise Immunity Characteristic of CMOS Devices
DW SUFFIXSOORDERING INFORMATION KK74LV240N Plastic KK74LV240DW SOIC TA = -40° to 125° C for all packages LOGIC DIAGRAM 1A01A11A21A32A02A12A02468111315 181614129753 PIN 20=VCC PIN 10 = GND 1Y01Y11Y21Y32Y02Y12Y02Y1PIN ASSIGNMENT 1OE1A02Y31A1INVERTINGOUTPUTS12345678910 20191817161514131211VCC2OE1Y02A31Y12A21Y22A11Y32A0DATAINPUTS2Y21A22Y11A32Y0GND2A117OUTPUTENABLES1OE2OE119FUNCTION TABLE Input Output nOE nAn L L L H H X H= high level L = low level X = don’t care Z = high impedance nYn H L Z
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KK74LV240
MAXIMUM RATINGS*
Symbol Parameter VCCIIK *1IOK *2IO *3ICCIGNDPD
DC supply voltage DC Input diode current DC Output diode current DC Output source or sink current DC VCC current DC GND current
Power dissipation per package: *4 Plastic DIP SO
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds
-0.5 to +5.0
±20 ±50 ±35 ±70 ±70 750 500 -65 to +150
260
V mA mA mA mA mA mW
Value Unit Tstg TL
*
°C °C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit VCCVIVOTAtr, tf
DC Supply Voltage Input Voltage Output Voltage
Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC =1.2 V
VCC =2.0 V VCC =3.0 V VCC =3.6 V
1.2 0 0 -40 0 0 0 0
3.6 VCCVCC+125 1000 700 500 400
V V V °C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
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KK74LV240
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Test VCCSymbol Parameter VIH
HIGH level input
voltage
conditions V 25°C
minmax
0.9
1.42.12.5- - - - 1.11.922.923.522.48- - - -
- - - - 0.30.60.91.1- - - -
Guaranteed Limit -40°C to 85°C min0.9 1.4 2.1 2.5 - - - - 1.0 1.9 2.9 3.5
max- - - - 0.3 0.6 0.9 1.1 - - - -
125°C min 0.9 1.4 2.1 2.5 - - - - 1.0 1.9 2.9 3.5
max - - - - 0.3 0.6 0.9 1.1 - - - -
Unit V
1.22.03.03.6 1.22.03.03.6
1.22.03.03.63.01.22.03.03.63.0* 1.2*
VIL
LOW level input voltage
V
VOH
HIGH level output VI = VIH or VIL voltage IO = -50 µА
V
VOL
LOW level output voltage
VI = VIH or VIL IO = -8 mА VI = VIH or VIL IO = 50 µА
- 2.340.090.090.090.09
- - - -
- 2.20 - V 0.1 0.1 0.1 0.1
- - - -
0.1 0.1 0.1 0.1
V
IIIOZ
Input current
VI = VIH or VIL IO = 8 mА VI = VCC or 0 V
- 0.33- -
±0.1±0.5
- 0.4 - 0.5 V - -
±1.0±5
- -
±1.0 ±10
µА µА
Three state leakage 3-state outputs current VI (01,19) = VIH
VO =VCC or 0 V Supply current
VI =VCC or 0 V IO = 0 µА
ICC* - 8.0- 80 - 160 µА
* VCC = 3.3 ± 0.3 V
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KK74LV240
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns)
Test VCCSymbol Parameter conditions V 25°C tPHL, tPLHPropagation delay , 1An to VI = 0 V or VCC 1.21Yn, 2An to 2Yn Figure 1 and 3 2.0* tPHZ tPLZPropagation delay, 1OE to VI = 0 V or VCC 1.21Yn, 2OE to 2Yn Figure 2 and 4 2.0* tPZH tPZLPropagation delay, 1OE to VI = 0 V or VCC 1.21Yn, 2OE to 2Yn Figure 2 and 4 2.0* tTHL, tTLHOutput Transition Time, Any Output CICPDInput capacitance Power dissipation capacitance (per one channel) VI = 0 V or VCC 1.2Figure 1 and 3 2.0* VI = 0 V or VCC3.0 - - - - - - - - - - - - - - 1002415140302014032206016107.050Guaranteed Limit -40°C to 85°C max 125 30 19 175 35 24 175 40 25 75 20 13 - - - - - - - - - - - - - - - - - - - - - - - - 125°C min max150 36 23 210 41 28 210 48 30 90 24 15 Unit ns minmaxminns ns ns - 7.0 - 7.0 pF - - - - pF * VCC = 3.3 ± 0.3 V
tr1An or 2An10%90%50%tfVCCGNDtPHL1OE or 2OEtPZL 1Yn or 2Yn50%VCCtPLZ50%GNDVCCtPLH1Yn or 2YntTHL90%50%10%tPZHtPHZ50%VOLVOHGNDtTLH 1Yn or 2Yn
Figure 1. Switching Waveforms
TEST POINTDEVICEUNDERTESTTEST POINT1 kCL*Figure 2. Switching Waveforms
OUTPUTCL*DEVICEUNDERTESTOUTPUTConnect to VCC whentesting tPLZ and tPZLConnect to GND whentesting tPHZ and tPZH
* Includes all probe and jig capacitance
Figure 3. Test Circuit
* Includes all probe and jig capacitance
Figure 4. Test Circuit
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KK74LV240
N SUFFIX PLASTIC DIP(MS - 001AD)ADimension, mm2011B110SymbolABCMIN24.896.1MAX26.927.115.33FLDF0.361.142.547.620°2.927.620.20.380.561.78C-T-SEATINGNGD0.25 (0.010) M TKPLANEGHHJMJKLMN10°3.818.260.36NOTES:1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.D SUFFIX SOIC(MS - 013AC)A2011Dimension, mmSymbolMIN12.67.42.350.330.41.279.530°0.10.23100.258°0.30.3210.650.75MAX137.62.650.511.27HBPAB1G10CR x 45CDF-T-D0.25 (0.010) M TCMKSEATINGPLANEJFMGHJKMPRNOTES:1. Dimensions A and B do not include mold flash or protrusion.2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side.
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