Method of fabricating an integrated circuit

专利名称：Method of fabricating an integrated circuit发明人：Steffen Meyer,Rolf Weis,Burkhard

Ludwig,Christoph Noelscher

申请号：US11843052申请日：20070822公开号：US07759242B2公开日：20100720

专利附图：

摘要：A method of fabricating an integrated circuit, including the steps of forming afirst mask layer in the form of a hard mask layer including a plurality of first openings anda second mask layer with at least one second opening which at least partially overlaps

with one of the first openings, wherein the at least one second opening is generatedlithographically; and at least two neighboring first openings are distanced from eachother with a center to center pitch smaller than the resolution limit of the lithographyused for generating the second opening.

申请人：Steffen Meyer,Rolf Weis,Burkhard Ludwig,Christoph Noelscher

地址：Dresden DE,Dresden DE,Munich DE,Nuremberg DE

国籍：DE,DE,DE,DE

代理机构：Slater & Matsil, L.L.P.

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