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基于FPGA的万年历电路的设计
学 校： 系 部： 专 业： 年 级： 学生姓名： 学 号： 指导教师：
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Based on the design of the calendar FPFA circuit
University： Department： Specialty: Class: Student’s Name: Student’sNumber: Faculty Adviser:
目录
摘要 ............................................................................................................................... I
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Abstract ......................................................................................................................... II 前言 ............................................................................................................................... 1 第1章 万年历的发展及FPGA简介 ........................................................................... 2 万年历的发展 ............................................................................................................... 2 FPGA简介 ...................................................................................................................... 2 第2章 设计原理 ......................................................................................................... 3 组成模块 ....................................................................................................................... 3 系统设计图 ................................................................................................................... 3 第3章 各功能模块介绍 ............................................................................................. 5 分频模块（fenpin） ................................................................................................... 5 控制模块（countr） ................................................................................................... 5 时间显示调整模块（mux_4） ..................................................................................... 5 时分秒模块 （timeve） ............................................................................................. 6 年月日模块（nyr2009） ............................................................................................. 6 显示控制模块(mux_16) ............................................................................................... 7 译码器（yimaqi） ....................................................................................................... 7 第4章 模拟仿真 ......................................................................................................... 9 年月日模块仿真 ........................................................................................................... 9 时分秒模块仿真 ........................................................................................................... 9 结论 ............................................................................................................................. 10 总结与体会 ................................................................................................................. 11 谢辞 ............................................................................................................................. 12 参考文献 ..................................................................................................................... 13 附录一 ......................................................................................................................... 14 附录二 ......................................................................................................................... 25 附录三 ......................................................................................................................... 31
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基于FPGA的万年历电路的设计
摘要
基于FPGA的万年历设计，主要完成的任务是使用Verilog语言，在Quartis2上完成电路设计，程序开发模拟，基本功能是能够显示/修改年月日时分秒。电路设计模块中分为几个模块：分频、控制、时间显示调整、时分秒、年月日、显示控制、译码器。各个模块完成不同的任务，合在一起就构成了万年历的系统电路设计。至于程序编写，使用Verilog语言，根据各个模块的不用功能和它们之间的控制关系进行编写。软件模拟直接在Quartis2上进行。
进入信息时代，时间观念越来越重，但是老式的钟表以及日历等时间显示工具已经不太适合。如钟表易坏，需要经常维修，日历需要每天翻页等。对此，数字万年的设计就有了用武之地。基于FPGA的万年历设计，采用软件开发模拟，开发成本低，而且再功能设计上有很大的灵活度，只要在软件上进行简单的修改就能实现不同的功能要求，能够满足不同环境要求。同时，该设计在精确度上远远超过钟表，并且不需要维修，也不用像日历一样每天翻页，极其方便，且能够添加各种不同功能的要求。例如：在万年历上添加闹钟，同时显示阴阳历等。综上所述本设计具有设计方便、功能多样、电路简洁、成本低廉等优点，符合社会发展趋势，前景广阔。
关键词：万年历，日历，FPGA，Verilog，Quartus2
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Based on the design of the calendar FPFA circuit
Abstract
The calendar based on FPGA design, the main task is to use Verilog language, in the Quartis2 complete circuit design, program development, basic function is simulated when able to display date/modify minutes. Circuit design module is divided into several modules: points frequency, control and time display adjustment, arc, date, display when control, decoder. Each module complete different tasks, together they form a calendar system circuit design. As for programming, Verilog language, according to use the modules without function and the relations between them control compilation. Software simulation on directly in Quartis2.
Into the information age, the concept of time is more and more heavy, but old-fashioned clock and calendar etc time display tools are not very good.
Key Words: Calendar, calendar, FPGA, Verilog, Quartus2
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前言
随着近年来科学技术的迅速发展和普及，我们的工作，生活观念也发生了巨大的改变，人们对各式电子产品的要求也越来越高，使得与生活密切相关的电子万年历逐渐走向智能化、便捷化。每到新年，人们就会买来一本新的日历，配上绘有图画的日历牌挂在墙上，既是装饰，又能指示年、月、日、星期等信息。但使用这种纸质日历，必须记得每天按时撕一张，否则反而会记错日期，常常有人因为忘记每天撕掉而记错日期，错过重要事情，造成损失。与传统纸质的万年历相比,数字万年历得到了越来越广泛的应用。
本设计基于FPGA，采用Verilog 语言编程,用软件的方式设计,灵活性好,且作为课程设计来说不仅是对以往大学阶段一些知识的应用也不用花费多少成本。按照系统设计功能的要求,设计一个简单的数字万年历，显示年、月、日、时、分、秒等基本功能。对此国内外许多设计人员对其进行了大量的设计，有用单片机开发的，有用FPGA开发的。由于使用FPGA设计、简便，成本低廉，所以本课程设计采用基于FPGA开发。在设计过程中要完成年月日时分秒等基本功能，同时还要设计闹钟功能以及阴阳历显示功能（这个是国外设计爱好者未考虑的）。采用FPGA设计的万年历由于成本低，精度高，可靠性好等优点，使它有了非常广阔的使用之处。
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第1章 万年历的发展及FPGA简介
万年历的发展
钟表、日历等的数字化大大方便了现代人的生活，同时也大大的扩展了钟表的功能，例如自动报警、打铃、控制其他电子产品等。而这些功能的实现，均是以钟表的数字化为基础的。因此，研究数字万年历及扩大其应用，有非常现实的意义。数字万年历是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和灵活性，且无机械装置，具有更长的使用寿命，因此得到了广泛的使用。数字万年历从原理上讲是一种典型的数字电路，其中包括了组合逻辑电路和时序电路。
此次设计与制做数字万年历就是为了了解数字钟的原理，从而学会制作数字钟。而且通过万年历的制作进一步了解各种在制作中用到的中小规模集成电路的作用及使用方法，且由于电子万年历包括组合逻辑电路和时序电路，通过它可以进一步学习与掌握各种组合逻辑电路与时序电路的原理与使用方法。
FPGA简介
FPGA是现场可编程门阵列（Field programmable gates array）的英文简称，是由
可编程逻辑模块组成的数字集成电路（IC）,这些逻辑模块之间用可配置的互联资源。设计者可以对这些器件进行编程来完成各种各样的任务。由于实现方式的不同，有些FPGA只能编程一次，而有些则可以重复进行多次编写。在FPGA名称中的“现场可编程”是指“在现场”进行。与那些内部功能已被制造者固化的器件相反。由于FPGA的设计成本低廉，修改方便，从而催生了的、许多富有创新意识的公司，这就意味着设计人员可以在基于FPGA的测试平台上实现他们的软件开发，而不需要承担数额巨大的不可重现工程的成本或昂贵的开发工具。
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第2章 设计原理
组成模块
万年年来设计要完成的基本功能是显示年月日时分秒以及时间修改功能，对此需要把系统分为以下几个模块：分频模块（fenpin）、控制模块（contr）、时间显示调整模块（mux_4）、时分秒模块（timeve）、年月日模块（nyr2009）、显示控制模块（mux_16）、译码器模块（yimaqi）。分频模块是为了得到一个周期为秒的脉冲，该脉冲主要用于秒的走动；控制模块要完成的功能是由使用者决定显示年月日还是时分秒，当使用者不参与控制时，时分秒和年月日每隔一小段时间会自动轮流显示，当使用者参与控制时则需要由改模块完成；时间显示调整模块，顾名思义就是对时间进行调整修改；时分秒模块和年月日模块分别控制时分秒和年月日；显示控制模块的功能是控制显示时分秒还是年月日，在设计过程中为了节省器材，减少数码管的个数，把年月日和时分秒分成两个模块，至于显示哪一个则有该模块完成任务；译码器则是在数码管上显示当前时间。
系统设计图
图1 流程图
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图2 功能设计图
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第3章 各功能模块介绍
分频模块（fenpin）
该模块的主要功能是想得到一个时钟频率为1Hz的一个脉冲，也就是说想得到周期为1秒的一个脉冲。设计思路是：用一个模10计数器，该计数器每秒有10个脉冲波形，如图3所示：
图3 模10计数器波形
然后对该计数器每秒计数一次，也就是说在一秒内有10个脉冲，但是只要最后的
一个脉冲，这样就得到了一个周期为1s的脉冲，如图4所示：
图4 1Hz脉冲
控制模块（countr）
该模块的主要功能是对时间显示调整模块（mux_4）进行控制，并且参与外部控制。设计思路：在没有按下外部控制按键时，每8秒轮流控制年月日和时分秒模块，就是说在前8秒内令rc为0，下一个8秒内令其为1，然后轮流交换。rc的作用就是相当于个脉冲，这个脉冲决定了该模块的输出电平。当按下外部按键的时候，也就意味着使用者参与控制了，该模块有2个外置按键可供使用者使用，按下第一个按键则显示时分秒，按下第二个按键显示年月日，当两个按键都按下的时候默认按键无效。
时间显示调整模块（mux_4）
该模块的功能是控制显示器，决定显示年月日还是时分秒。[为了节省数码管，该
设计把年月日和时分秒的显示分开]，当该模块接受到低电平时显示当前的时分秒，当
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接受到的是高电平时则显示年月日。
时分秒模块 （timeve）
秒（second）：秒信号qm[7:0],低四位qml[3:0]，高四位qmh[7:4]，秒进位信号enmin。给予秒信号和进位信号一个初始值，令{qmh,qml}=0,carry1=0。当秒信号计数到59时，则要把秒信号计为0，同时进位信号carry1=1。当秒信号计数小于59时，如果十位qmh==5，个位qml<9则十位不变，个位每秒加1， carry1=0；如果qmh<5而qml==9,则令qmh=qmh+1,qml=0,carry1=0；如果qmh<5且qml<9，则qmh=qmh，qml=qml+1,carry1=0。最终秒信号qm={qmh,qml},秒进位信号enmin =carry|jf(jf是外部按键信号)。
分（minute）：分信号qf[7:0]，低四位qfl[3:0]，高四位qfh[7:0]，分进位信号enhour。给予初始值：{qfh,qfl}=8’h00,进位信号carry1=0。当分信号计数到59时，则令{qfh,qfl}=8’h00，carry1=1。如果qfh==5,qfl<9，则qfh=qfh，qfl=qfl+1，carry1=0。
如果qfh<5，qfl==9，则qfh=qfh+1，qfl=0，carry1=0；如果qfh<5，qfl<9，则qfh=qfh，qfl=qfl+1，carry1=0。最终分信号qf={qfh,qfl}，分进位信号enhour =carry1|jh(jh同秒信号中的jf，一样是外部按键信号)。
时（hour）：时信号qs[7:0]，低四位qsl[3:0]，高四位qsh[7:0]，时进位信号cout。初始赋值令{qsh,qsl}=8’h00，进位信号carry1=0。则当时信号计数到23(qsh==2&& qsl=3)，则{}=8’h00，carry1=1；如果qsh=2，qsl<3，则 qsh=qsh，qsl=qsl+1，carry1=0；如果qsh<2，qsl=9，则qsh=qsh+1，qsl=0，carry1=0；如果qsh<2，qsl<9则qsh=qsh，qsl=qsl+1，carry1=0。最终时信号qs={qsh,qsl}，cout=carry1。
年月日模块（nyr2009）
日计数：日信号qr[7:0]，日进位信号clky，以及每月天数date。date：一年又十二个月，而且每个月的天数不完全相同，需要对date做不同的取值判断。给一个月计数qy，由月计数的不同给予date不同取值。如：当qy=3，则date=31。这里有个需要注意
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的是2月，一般年份2月有28天，但是闰年则有29天。对于日信号，当qr=date时，则令qr=1，clky=1；否则若日信号的十位与date的十位相同且个位小于date的个位，则十位不变，个位每个脉冲加1（这里的秒冲有外界和内部两种，内部脉冲来自时分秒模块的输出cout）；若日信号十位小于date的十位，但是个位相等，则令十位加1，个位计为0；若日信号十位和个位均小于date则令日信号十位不变，个位加1。.
月计数和年计数大致计算方法和日的差不多，只不过月计数的时钟脉冲来自日计数的进位信号，而年计数的脉冲来自于月计数的进位信号。需要注意的是日和月都是两位十进制数表示，故需要用8位二进制数表示，而年是四位十进制信号，需要16位表示。这里不再多说。
显示控制模块(mux_16)
该模块的主要功能是控制是显示时分秒还是年月日。设计思路：根据控制模块
（contr）的输出k的高低电平决定。当k是高电平时，该模块的输出端输出的是当前的时分秒信号，即：令q0=0、q1=0，q2、q3显示秒信号的十位与个位，q4、q5显示分信号的十位与个位，q6、q7显示时信号的十位与个位。当k是低电平时，该模块的输出端输出的是年月日，即：令q0、q1、q2、q3显示年信号的千位、百位、十位、个位，q4、q5显示月信号的十位与个位，q6、q7显示日信号的十位与个位。
译码器（yimaqi）
译码器可以将输入代码的状态翻译成相应的输出信号，以高、低电平的形式在各自的输出端口送出，以表示其意愿。译码器有多个输入端和多个输出端。假如输入的端个数为，每个输出端只能有两个状态，则输出端个数最多有2n个本设计采用的是3线-8线译码器，输入端为年月日的信号或者是时分秒的信号，输出的8位二进制数对应译码器的真值表。
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第4章 模拟仿真
年月日模块仿真
该仿真图显示的是09年5月分的，由图可以看出5月分有31天，当月份进入到下一个月的时候，日期day则变为1号，仿真结果无误。
时分秒模块仿真
上图显示的是时分秒模块的运行仿真结果图，秒针每到60个计数时分针才走动一次，秒针的走动需要由分频模块输出的1HZ的脉冲来带动，秒带分走，分带时走。秒计数最大到59时分计数加1，分也是到59时计数加1。
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结论
每到新年，人们就会买来一本新的日历，配上绘有图画的日历牌挂在墙上，既是装饰，又能指示年、月、日、星期等信息。但使用这种纸质日历，必须记得每天按时撕一张，否则反而会记错日期，常常有人因为忘记每天撕掉而记错日期，错过重要事情，造成损麻烦。与传统纸质的万年历相比,数字万年历得到了越来越广泛的应用。本文是一篇基于FPGA的数字万年历的论文，在设计过程中我通过在网上和图书馆查阅资料，收集了大量相关方面的资料，通过对这些资料的学习，我了解了FPGA的相关知识并认真复习了Verilog语言。本次毕业设计除了让我回顾以前学过的知识外，也使我学习到了新的东西。这次毕业设计可以说是对四年的大学学习的总结。
本次毕业设计完成的主要工作和任务如下：对设计方案的理论研究，电路原理的设计制作，软件的编写和调试以及毕业论文的制作。
通过对本课题的研究我有以下几个方面的收获：
（1）学习与掌握了FPGA的基本原理及其各种应用，对它的软件设计方法有较深入的认识。
（2）通过对电路原理图设计绘制，对数字电路有了更加清晰的了解，学到了以前没注意到的知识。
（3）本设计重点在于软件的设计，因此在设计过程中使自己在大学学到的Verilog语言知识得到了巩固，同时提高了解决实际问题的能力
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总结与体会
通过几个月的努力，万年历设计基本完成了所要实现的功能，完成了毕业设计。在这次的设计过程中主要是在Quartus2上使用Verilog语言完成代码的编写与模拟仿真，在设计过程中出现了不少的问题，一些问题是因为自己的粗心大意，也有一些问题则是对相关知识的认识不够彻底。通过对这些问题的解决处理，我感觉到不仅所学知识有了较全面的了解，同时也是对我自身的一个进步。比如开始我没能认真书写导致出现不少错误字符，没能及时保存导致文档丢失等，这些问题的发现解决我相信对我以后进入社会，参加工作是一个很好的锻炼。
当然在设计过程中也遇见了不少自己解决不了的问题，对此我很感谢我的老师、同学们的帮助。他们的帮助不仅使我顺利解决问题，同时也使我感受到了温暖，给了我强大的动力，使我和同学们的关系更加紧密，使我更加深入明白了团结就是力量。我相信在以后的人生道路上，我将不会迷茫，因为我知道我不能解决的问题不一定是不能解决的问题，这一点我坚信。
最后我想说的是我又一次感受到了书到用时方恨少。在大学期间学院给我们专业开了不少课程，自己没怎么认真学习，这一点在平时没怎么感受，但是在这次的毕业设计中我我却感受到了。毕业设计是对大学以往知识的综合运用，但是由于学习的不够认真，导致这设计过程中遇见了很多看似简单却没法自我完成的问题。
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谢辞
该毕业设计在一定程度上代表了我大学四年所学，也是我大学生活的一个结束，为此我想在这里感谢学院为我带来的一切，没有学院为我提供的这个平台，我想将会很难顺利地完成大学四年的学习和本次毕业设计。
该论文是在我的毕业设计指导老师x老师的亲切、热心的指导下完成的。x老师的热心给予的完成毕业设计的动力，x老师的帮助使我客服了诸多困难，最终在老师的指导下我完成了毕业设计，再次我要深深的感谢她。
同时，我还要感谢x老师，在做毕业设计的过程中我深深的感到了在去年和x老师一起学习Quartus2对于我的毕业设计是多么的有用。所以我要感谢x老师。
在设计之初，我的迷茫曾一度让我烦闷，不知道该怎么写，不知道怎么下手，在这个困难时期，各位老师和同学给了我很大的帮助，使他们的帮助使我一步步的完成了毕业设计。在这里请接受我真诚的谢意！
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参考文献
[1] 刘建清，刘汉文，高光海，等，从零开始学CPLD和VerilogHDL编程技术[M]，北京：国防工业出版社，2006；
[2] 杨春玲，朱敏，等，可编程逻辑器件应用实践[M]，哈尔滨：哈尔滨工业大学出版社，2008 [3] 冯涛，王程，等，可编程逻辑器件开发技术——MAX+plus2入门与提高[M]，北京：人民邮电出版社，2002
[4] 杜海生，邢文等，FPG设计指南器件、工具和流程[M]，北京：人民邮电出版社，2007
[5] 王辉，殷颖，陈婷，俞一鸣，等，MAX+plus2和Quattur2应用于技巧开发[M]，北京：机械工业出版社，2007
[6] 张志刚，等，FPGA于SOPC设计教程——DE2实践，西安：西安电子科技大学出版社，2007
[7] 夏宇闻，等，Verilog数字系统设计教程（第2版）[M]，北京：北京航空航天大学出版社，2008 [8] 郑利浩，王荃，陈华锋，等，FPGA数字逻辑设计教程——Verilog[M]，北京：电子工业出版社，2010
[9] 夏宇闻，甘伟，等，Verilog HDL入门(第3版)[M]，北京：北京航空航天大学出版社，2008 [10]吴厚航，等，深入浅出玩转FPGA[M]，北京：北京航空航天大学出版社，2005 [11]吴继华，王诚，等，Altera FPGA/CPLD设计（基础篇），北京：人民邮电出版社，2011 [12] EDA先锋工作室，吴继华，蔡海宁，王诚，等，Altera FPGA/CPLD设计（高级篇）（第2版），北京：人民邮电出版社，2011 [13]（美）沃尔夫（Wolr,W.），等，基于FPGA的系统设计[M]，北京：机械工业出版社，2005
[14]姚远，李辰，等，FPGA应用开发入门与典型实例（修订版）[M]，北京：人民邮电出版社，2010 [15]侯伯亨,等，VHDL硬件描述语言与数字逻辑电路设计（第三版）[M]，西安：西安电子科技大学出版社，2009
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附录一
At present by the hardware description language (Verilog or VHDL) has done
by a simple circuit design, can the comprehensive and layout, rapid replication to test, is on the FPGA design verification of modern IC technical mainstream. These can edit component can be used to achieve some basic logic gate (such as AND, OR, XOR, NOT) OR a bit more complicated combination function such as decoder OR mathematical equations. In most of the FPGA inside, these editable components are contains memory components such as flip-flop Flip flop) - (or other more complete memory blocks.
System according to need stylist can be connected by editable the FPGA internal logic, like connecting block a circuit test plate is placed on a chip. A after they leave the finished product FPGA logic blocks and connection can be changed according to the designers, so the FPGA can complete need logical functions.
The FPGA in general than ASIC (special integrated chips) speed will slow, unable to perform complex designs, and consume more power. But they also have many advantages such as can quickly finished product, can be modified to correct an error in a programme and cheaper cost. Manufacturers might also offer cheap but editing ability is poor FPGA. Because these chips have more bad of the editable ability, so these design development is in ordinary FPGA completion, and then on to design transferred to a similar to the chip ASIC. Another method is to use CPLD (complex programmable logic device prepare).
Early in the mid 1980s PLD equipment in FPGA has root. CPLD and FPGA includes some relatively large number of programmable logic unit. CPLD logical gate density in a logical units to tens of thousands, and FPGA is usually between in tens of thousands to millions of.
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The major difference between and FPGA CPLD their system structure. CPLD is a bit of restrictive structure. This structure by one or more editable results logical groups of the sum of gilead and some relatively low amounts of locking registers. The result is that lack of editing flexibility, but there can be expected to delay time and logic unit link units a high rate of advantages. And there are many connection FPGA is, so although let it unit can be more flexible editor, but the structure are much more complex.
CPLD and FPGA another difference is most FPGA contain high levels of built-in module (such as adder and on time-multiplier) and built-in memory. A so the important difference is concerned, many new FPGA support full or part of the system in a configuration. Allow their design with system upgrades or dynamic reconfigured and change. Some FPGA can let equipment edit and part of the normal operation. Other parts continue.
By the Logic element Array FPGA LCA (Array) such a Cell questions concept, internal including Configurable Logic module which CLB (Configurable questions) and Output Input module which Output IOB (Input) and internal attachment (Interconnect) three parts. Field programmable gates array (FPGA) is programmable devices. And the traditional logic circuit and the gate array (such as PAL GAL and CPLD device), compared with different structure, the FPGA, FPGA with small look-up table (16 x 1RAM) to realize the combination of logic, each look-up table connected to a D flip-flop input and trigger again drive other logic circuit or driver I/O, which constitutes the assembly logic functions can be realized and realize the basic logic sequential logical function module, these module unit by using metal connection between interconnected or connected to the I/O modules. The logic is through FPGA inward.
Current main FPGA is still based on look-up table technology, has far exceeded the previous version of the basic performance, and integrate the common functions (such as RAM, clock management and the hardcore (DSP) ASIC type) module. The FPGA chip partially completed by 7 to Lord, respectively: programmable
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input/output unit, basic programmable logic unit, complete clock management, embedded pieces type RAM, rich wiring resources, embedded bottom function units and inline dedicated hardware modules. The function of each module are as follows:
1. Programmable input/output unit (IOB)
Programmable input/output unit referred to as I/O unit, is the interface with external circuit chip, complete different part electrical characteristics of input/output signal driver and matching requirements, its beckoned structure shown as shown in figure 1-2. The I/O within the FPGA in groups, each of classification can be independently support different I/O standards. Through the flexible configuration software can fit different electrical standards and I/O physical properties, can adjust the drive current size, can change, pulldown resistor. At present, the frequency of I/O port more and more is also high, some high-end FPGA technology can support by DDR 2Gbps registers as the data rate.
External input signal can through the storage unit IOB module input into the FPGA interior, may also enter the FPGA internal. When external input signal after IOB module ? the storage unit.
To facilitate the management and adapt to a variety of electric equipment standard, FPGA IOB was divided into the several group (the somebody), each by its interface standard somebody VCCO decision, a interface voltage somebody there can be only one of VCCO, but different VCCO can differ to somebody. Only the same electrical standard ports to connect together, VCCO voltage is the basic condition of interface standards.
2. Configurable logic block (CLB)
CLB is the basic logic unit within the FPGA. The actual number of CLB of the device and the characteristic will depend on different and different, but each CLB contains a configurable, the matrix switching matrix by four or six input, some selection circuits (multiplexing machines etc) and trigger composition. A switching matrix is highly flexible, open to configuration so
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that treatment combinations logic, the shift register or RAM. Xilinx FPGA device in the company, by multiple (CLB is generally four or 2) the same Slice and additional logic structure, as shown in figure 1-3 below. Each CLB module can not only used to implement the combinational logic, temporal logic, also can be configured to distributed RAM and distributed ROM. Xilinx Slice is the basic logic unit the definition, its internal structure as shown in figure 1-4 shows, a Slice of by two 4 functions, binary input in logic, calculate ?
3. Digital clock management module (DCM)
This provides the most FPGA digital clock management (all have Xilinx FPGA nature of this). Xilinx FPGA provide the most advanced launched digital clock management and phase lock loop. Phase lock loop can provide precise clock comprehensive, and can reduce jitter, and realize the filter function.
4. Embedded blocks RAM (BRAM)
Most FPGA have nested block RAM, which greatly expand the application range of the FPGA and agility. Block RAM can be configured to single port RAM, two-port RAM, content address memory (CAM) and FIFO storage structure some. RAM, FIFO is the concept of is popular in this was not redundant, description. CAM memory in its internal every single YuanZhongDou has a comparatively stored data in logic, writing CAM and internal each data, and returns compared with all the same port data, thus the address of data in the routing address switch is widely used. In addition to block RAM, still can place the LUT flexibly FPGA RAM and ROM and configured structures such as FIFO. In practical application, the number of RAM chip internal pieces of choice chip is an important factor.
Monolithic block RAM has a capacity of 18k bits, took the wide for 18 to bits, depth for 1024, and may, according to needs to change its position, but should satisfy harnessed two principles: first, the revised capacity (a wide depth) is not greater than 18k bit; Secondly, a wide cannot exceed 36 biggest bits. Of course, can be more pieces of block RAM cascade up to form larger RAM, now only limited by the number of RAM chip inside block, and no longer subject
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to two above principle constraint.
5. Rich wiring resources
Wiring resources connected all the units inside the FPGA, and the length of the attachment and process determines the signal on the wire transmission speed and driving ability. The FPGA chip has a wealth of wiring resources inside, according to the process, length, width and distribution in different position and are divided into four kinds of different categories. The first kind is global wiring resources, used for chip inside global clock and global reset/buy a wiring; The second type is long-term resources to complete chip speed signals between somebody and 2 of the clock signal wiring; global The third category is short term resources used to complete basic logic unit, the logical interconnection between and wiring; The fourth category is distributed wiring resources, used for proprietary clock and reset the control signal.
In practice, designers don't need direct selection wiring resources, layout wiring device can automatically according to the input logic nets table topology and constraint condition selecting wiring resources to connect each module unit. Essentially, wiring resources use method and the results of the design, direct relationship is closely.
6. Underlying inline function units
Inline function module mainly refers to the DLL Locked Loop (PLL), tow vehicle Phase Locked Loop), (soft processing DSP and CPU SoftCore nucleus (). Now more and more rich inline function units, makes the monolithic FPGA became system-level design tools, make its have the ability of the software and hardware joint design, gradually transition to the SOC platform. The DLL and with similar functions, PLL can be completed in high precision, low jitter clock frequency multiplication of and points frequency, and occupies emptiescompared to adjust and remove equal function. Xilinx company produces the chip, Altera DLL used to become the company's chip integrated, Lattice company's new PLL chip and integrated with DLL PLL. DLL used PLL and by IP core generated tools convenient
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to management and configuration.
7. Embedded special hardcore
Embedded special hardcore is relatively low-level embedded soft nuclear speaking, means the FPGA processing ability strong hardcore (Core), equivalent to hard-core ASIC circuit. In order to improve the FPGA performance, chip producers in the chip inside integrated some special hard core. For example: in order to improve the multiplication of speed, mainstream FPGA are integrated in the FPGA special on time-multiplier; In order to apply communications bus and interface standards, many high-end FPGA internal are integrated strings and transceiver (SERDES), can achieve dozens of Gbps speed of delivery. The high-end product not only Xilinx company has integrated Power PC series CPU, still embedded with DSP Core modules, its corresponding system-level design tools are EDK and Platform, according to this Studio forward Chip System (System on the concept of Chip cluster generator attempts. Through Miroblaze, Picoblaze PowerPC, such as the platform, can develop standards and its associated applications DSP .
The FPGA design precautions：
Whether you are a logical designers, hardware engineer or system engineer, or even with all these titles, as long as you in any kind of high-speed and more complex systems use agreement the FPGA, you will probably need to resolve device configuration, power management, IP integration, signal integrity and some of the other key design issues. However, you don't have to face these challenges alone, because in the current leading FPGA company application engineers every day to solve these problems, and they have put forward some amaze your design work easier design guiding principles and solutions. The I/O signal distribution
Can provide the most multifunctional pins, I/O standards, termination scheme and difference right FPGA in signal distribution are the most complex design guiding principles. Although the Altera FPGA device no design guiding
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principles (because it realize rise compare easy), but the spirit of the FPGA design principles guiding thought is quite complex. But in either case, for I/O pins distribution, there are some signal to keep in mind is common steps:
1. Use an electronic data list all plans signal allocation, and their important properties, such as I/O standard, voltage, need termination methods and relevant clock.
2. Check with the manufacturer block/regional compatibility criteria. 3. Consider using the second spreadsheets formulate FPGA layout to determine what tube feet is a universal, which is dedicated, which support difference signal to the and global and local clock, which need reference voltage.
4. Utilizing the above two spreadsheets information and regional compatibility criterion, first distribution restricted the biggest signal to the extent the last distribution on pins, the smallest restricted. For example, you may need to distribution serial bus and the clock signal, because they usually only assigned to some special.
At this stage, considering writing a contains only port distribution of HDL files. Then through the use of suppliers of tools or using a text editor manually create a limit files, for I/O standards and increase the SSO necessary support information. Ready for these basic documents, you can run layout wiring tools to confirm whether overlooked some standards or made a wrong distribution. This will make you at the initial stage design and layout engineer working together, common planning the PCB's walk line, redundancy planning, heat dissipation problems and signal integrity. The FPGA tools may can provide help in these fields, and help you to solve these problems, so you must ensure that understanding your toolkit function. You consult a layout experts the later time, the more you .
Based on the design of three main consumption CMOS power: internal (to short circuit), leakage (static) and switch (capacitors). When a gate transient, VDD and ground connection between internal power consumption short-circuit. Leakage
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power is widespread CMOS process caused by the parasitic effect. And switch power consumption is load capacitance, discharge from the cause. Switch power consumption and short circuit power consumption together called dynamic power consumption. Underneath introduction reduce static power consumption and dynamic power design techniques.
The FPGA and CPLD, the identification and classification:
The FPGA and CPLD, the identification and classification is mainly according to its structure characteristics and working principle. Usually the classification method is: will form a structure to product the device called CPLD logical behavior, such as the Lattice of ispLSI series, Xilinx XC9500 series, Altera MAX7000S series and the Lattice (former Vantis) Mach series, etc. Will with querying method structure form logic behavior, such as Xilinx FPGA device called the SPARTAN series, Altera FLEX10K or the ACEX1K series, etc. Although the FPGA and CPLD are programmable ASIC devices, there are many common features, but because CPLD and FPGA structural differences have respective characteristics:
(1) more suitable for completing various algorithm CPLD device logic, and the combination of FP GA is more suitable for complete temporal logic. In other words, the FPGA is more suitable for flip-flop, and lots of structure is more suitable for CPLD limited and a rich trigger the structure of the product.
2 continuous type wiring structure of CPLD determines its temporal delay is uniform and predictable, and FPGA segmented wiring structure of decide their delayed unpredictability.
(3) than CPLD in programming FPGA even greater flexibility. CPLD by modifying with fixed logic functions within the even circuit to programming, FPGA mainly through change the internal connection wiring to programming; FP GA can be in logic, and CPLD is door in programming logical block programming.
(4) the FPGA integration has more than CPLD high, the complex cabling structure and logical realized.
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(5) than the FPGA use up more CPLD device convenience. CPLD programming using E2PROM or FASTFLASH technology, without external memory chips, simple to use. And FPGA programming information should be stored in external memory and method of use complex. The FPGA application:
1. In the circuit design. Application of the FPGA
Connect logic, control logic is FPGA early role larger field is the cornerstone of FPGA application. In fact in circuit design the difficulty of application of FPGA compare big this request or developers should have corresponding hardware knowledge (circuit knowledge) and software application ability (development tools) this talent shortage, often are always engaged in new technology, new product development successful product will become market based products for product designers mainstream applications in the near future, general and special IP design will become a popular profession! Make circuit design is the premise of must have certain hardware knowledge. At this level, dry on learning, of course, started quickly is very important, the good table more waits for no one circuit development is golden bowl.
2. The product design
The relatively mature technology is applied to certain areas such as communication, video, information processing and so on develop industry needs and can be industry customers accept product this aspect is mainly the FPGA technology and professional technique combined with the problem, and another is the interface problems with professional customers product design also includes professional tools products and civil products, the former, the latter focus on performance to price sensitive product design in order to realize the product function as the main purpose, FPGA technology is a means of realization in this field, the FPGA because have interface, control, function IP, characteristics such as embedded CPU conditions, implement a simple structure, Curing degree high, fully functional system product design will be the FPGA
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technology using the vast market, for great explosive demand space of technical personnel product design the demand is higher, but now is a long journey to the industry is in form \"starting team\" state, as long as join, promising product design is a professional development direction location, not simple hobbies can do it! Product design domain will foster a large number of enterprises and entrepreneurs, is a recent development hot and opportunities.
3. The system-level applications
System-wide application is with traditional computer technology FPGA realizing a FPGA, combining with the computer system such as version Xilinx V - 4, V - 5 series of FPGA, realize inline POWER PC CPU, then cooperate with various peripheral function, achieve a basic environment, in this platform run LINUX system such as the system also will support various standard peripherals and functional interfaces (such as image interface) this constitutes a FPGA large system for fast it is very helpful. This \"very strong fortress\" flavour early advantage is not necessarily very obvious system, similar to the ARM system circumstances but if can slowly the advantage of exerting FPGA, To gradually realize some characteristic system is also a kind of development direction. If in the system level applications, the developers don't have system expansion and development capabilities, but since programming is meaningless, of course, the device driver development is another kind of circumstance, make the system-level application seemingly high starting point, but do not have deep development ability, will probably become lovers, like a lot of people will do web but not called will programming similar above is some personal development, the hope can help wanted to learn the FPGA but very all bewildered thinking. The same reason This is a good profession, a very good personal success opportunity. But it is certainly a very competitive industry, the key to look the speed and depth and of course the market adaptiveness. The latest application:
Beijing time on December 30th 2010 news, American and British scientists
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have developed jointly one paragraph speed super fast computer chip, make the current desktop computing capacity improvement 20 times. The current personal computers use dual-core, 4 nuclear, 16 processors to perform various tasks. Now, U.S. and British researchers development the central processing unit (CPU) will 1000 kernel effective integration in a chip. The breakthrough in the next few years or to open a new era of ultra-high speed operation, make family users no longer have to slow computer system feel depressed. Although faster, but due to the new \"super\" computer energy far below the current computer, so more environmental protection.
The researchers used a technique called \"field programmable gates array\" (hereinafter referred to as \"the FPGA\") chip, making microchips like contain millions of transistors, and the transistor is as the basic component of any circuit. However, the FPGA chip can be installed to specific users and their function is not circuit in factory set good. That way, users can be divided into a \"small transistor requirements for each group\\"small group\" complete different tasks.
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（This article from：）
附录二
目前以硬件描述语言（Verilog 或 VHDL）所完成的电路设计，可以经过简单的综合与布局，快速的烧录至 FPGA 上进行测试，是现代 IC 设计验证的技术主流。这些可编辑元件可以被用来实现一些基本的逻辑门（比如AND、OR、XOR、NOT）或者更复杂一些的组合功能比如解码器或数学方程式。在大多数的FPGA里面，这些可编辑的元件里也包含记忆元件例如（Flip－flop）或者其他更加完整的记忆块。
可以根据需要通过可编辑的连接把FPGA内部的逻辑块连接起来，就好像一个电路试验板被放在了一个里。一个出厂后的成品FPGA的逻辑块和连接可以按照设计者而改变，所以FPGA可以完成所需要的逻辑功能。
FPGA一般来说比ASIC（专用）的速度要慢，无法完成复杂的设计，而且消耗更多的电能。但是他们也有很多的优点比如可以快速成品，可以被修改来改正程序中的错误和更便宜的造价。厂商也可能会提供便宜的但是编辑能力差的FPGA。因为这些芯片有比较差的可编辑能力，所以这些设计的开发是在普通的FPGA上完成的，然后将设计转移到一个类似于ASIC的芯片上。另外一种方法是用CPLD（复杂备）。
早在1980年代中期，FPGA已经在PLD设备中扎根。CPLD和FPGA包括了一些相对大数量的可编辑。CPLD逻辑门的密度在几千到几万个逻辑单元之间，而FPGA通常是在几万到几百万。
CPLD和FPGA的主要区别是他们的系统结构。CPLD是一个有点限制性的结构。这个结构由一个或者多个可编辑的结果之和的逻辑组列和一些相对少量的锁定的寄存器。这样的结果是缺乏编辑灵活性，但是却有可以预计的延迟时间和逻辑单元对连接单元高比
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率的优点。而FPGA却是有很多的连接单元，这样虽然让它可以更加灵活的编辑，但是结构却复杂的多。
CPLD和FPGA另外一个区别是大多数的FPGA含有高层次的内置模块（比如和乘法器）和内置的记忆体。一个因此有关的重要区别是很多新的FPGA支持完全的或者部分的系统内重新配置。允许他们的设计随着系统升级或者动态重新配置而改变。一些FPGA可以让设备的一部分重新编辑而其他部分继续正常运行。
FPGA采用了逻辑单元阵列LCA（Logic Cell Array）这样一个概念，内部包括可配置逻辑模块CLB（Configurable Logic Block）、输出输入模块IOB（Input Output Block）和内部连线（Interconnect）三个部分。 现场可编程门阵列（FPGA）是可编程器件。与传统逻辑电路和门阵列（如PAL，GAL及CPLD器件）相比，FPGA具有不同的结构，FPGA利用小型查找表（16×1RAM）来实现组合逻辑，每个查找表连接到一个D触发器的输入端，触发器再来驱动其他逻辑电路或驱动I/O，由此构成了即可实现组合逻辑功能又可实现时序逻辑功能的基本逻辑单元模块，这些模块间利用金属连线互相连接或连接到I/O模块。FPGA的逻辑是通过向内部静态存储单元加载编程数据来实现的，存储在存储器单元中的值决定了逻辑单元的逻辑功能以及个模块之间或模块与I/O间的连接方式,并最终决定了逻辑单元的逻辑功能以及各模块之间或模块与I/O间的联接方式,并最终决定了FPGA所能实现的功能, FPGA允许无限次的编程.
目前主流的FPGA仍是基于查找表技术的，已经远远超出了先前版本的基本性能，并且整合了常用功能（如RAM、时钟管理和DSP）的硬核（ASIC型）模块。FPGA芯片主 要由7部分完成，分别为：可编程输入输出单元、基本可编程逻辑单元、完整的时钟管理、嵌入块式RAM、丰富的布线资源、内嵌的底层功能单元和内嵌专用硬件模块。 每个模块的功能如下：
1． 可编程输入输出单元（IOB）
可编程输入/输出单元简称I/O单元，是芯片与外界电路的接口部分，完成不同电气特性下对输入/输出信号的驱动与匹配要求，其示意结构如图1-2所示。 FPGA内的I/O按组分类，每组都能够独立地支持不同的I/O标准。通过软件的灵活配置，可适配不同的电气标准与I/O物理特性，可以调整驱动电流的大小，可以改变上、下拉电阻。目前，I/O口的频率也越来越高，一些高端的FPGA通过DDR寄存器技术可以支持高
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达2Gbps的数据速率。 外部输入信号可以通过IOB模块的存储单元输入到FPGA的内部，也可以直接输入FPGA 内部。当外部输入信号经过IOB模块的存储单元输入到FPGA内部时，其保持时间（Hold Time）的要求可以降低，通常默认为0。
为了便于管理和适应多种电器标准，FPGA的IOB被划分为若干个组（bank），每个bank的接口标准由其接口电压VCCO决定，一个bank只能有 一种VCCO，但不同bank的VCCO可以不同。只有相同电气标准的端口才能连接在一起，VCCO电压相同是接口标准的基本条件。
2． 可配置逻辑块（CLB）
CLB是FPGA内的基本逻辑单元。CLB的实际数量和特性会依器件的不同而不同，但是每个CLB都包含一个可配置开关矩阵，此矩阵由4或6个输入、一些 选型电路（多路复用器等）和触发器组成。 开关矩阵是高度灵活的，可以对其进行配置以便处理组合逻辑、移位寄存器或RAM。在Xilinx公司的FPGA器件中，CLB由多个（一般为4个或2个）相同的Slice和附加逻辑构成，如图1-3所示。每个CLB模块不仅可以用于实现组合逻辑、时序逻辑，还可以配置为分布式RAM和分布式ROM。Slice是Xilinx公司定义的基本逻辑单位，其内部结构如图1-4所示，一个Slice由两个4输入的函数、进位逻辑、算术逻辑、存储逻辑和函数复用器组成。算术逻辑包括一个异或门（XORG）和一个专用与门（MULTAND），一个异或门可以使一个Slice实现 2bit全加操作，专用与门用于提高乘法器的效率；进位逻辑由专用进位信号和函数复用器（MUXC）组成，用于实现快速的算术加减法操作；4输入函数发生 器用于实现4输入LUT、分布式RAM或16比特移位寄存器（Virtex-5系列芯片的Slice中的两个输入函数为6输入，可以实现6输入LUT或 64比特移位寄存器）；进位逻辑包括两条快速进位链，用于提高CLB模块的处理速度。
3． 数字时钟管理模块（DCM）
业内大多数FPGA均提供数字时钟管理（Xilinx的全部FPGA均具有这种特性）。Xilinx推出最先进的FPGA提供数字时钟管理和相位环路锁定。相位环路锁定能够提供精确的时钟综合，且能够降低抖动，并实现过滤功能。 4． 嵌入式块RAM（BRAM）
大多数FPGA都具有内嵌的块RAM，这大大拓展了FPGA的应用范围和灵活性。块RAM可被配置为单端口RAM、双端口RAM、内容地址存储器 （CAM）以及FIFO等常用存储结
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构。RAM、FIFO是比较普及的概念，在此就不冗述。CAM存储器在其内部的每个存储单元中都有一个比较逻辑，写入 CAM中的数据会和内部的每一个数据进行比较，并返回与端口数据相同的所有数据的地址，因而在路由的地址交换器中有广泛的应用。除了块RAM，还可以将 FPGA中的LUT灵活地配置成RAM、ROM和FIFO等结构。在实际应用中，芯片内部块RAM的数量也是选择芯片的一个重要因素。
单片块RAM的容量为18k比特，即位宽为18比特、深度为1024，可以根据需要改变其位宽和深度，但要满足两个原则：首先，修改后的容量（位宽 深度）不能大于18k比特；其次，位宽最大不能超过36比特。当然，可以将多片块RAM级联起来形成更大的RAM，此时只受限于芯片内块RAM的数量，而 不再受上面两条原则约束。 5． 丰富的布线资源
布线资源连通FPGA内部的所有单元，而连线的长度和工艺决定着信号在连线上的驱动能力和传输速度。FPGA芯片内部有着丰富的布线资源，根据工艺、长度、宽度和分布位置的不同而划分为4类不同的类别。第一类是全局布线资源，用于芯片内部全局时钟和全局复位/置位的布线；第二类是长线资源，用以完成芯片 Bank间的高速信号和第二全局时钟信号的布线；第三类是短线资源，用于完成基本逻辑单元之间的逻辑互连和布线；第四类是分布式的布线资源，用于专有时钟、复位等控制信号线。 在实际中设计者不需要直接选择布线资源，布局布线器可自动地根据输入逻辑网表的拓扑结构和约束条件选择布线资源来连通各个模块单元。从本质上讲，布线资源的使用方法和设计的结果有密切、直接的关系。 1．电路设计中FPGA的应用
连接逻辑，控制逻辑是FPGA早期发挥作用比较大的领域也是FPGA应用的基石．事实上在电路设计中应用FPGA的难度还是比较大的这要求开发者要具备相应的硬件知识（电路知识）和软件应用能力（开发工具）这方面的人才总是紧缺的，往往都从事新技术，新产品的开发成功的产品将变成市场主流基础产品供产品设计者应用在不远的将来，通用和专用IP的设计将成为一个热门行业！搞电路设计的前提是必须要具备一定的硬件知识．在这个层面，干重于学，当然，快速入门是很重要的，越好的位子越不等人电路开发是黄金饭碗． 2．产品设计
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把相对成熟的技术应用到某些特定领域如通讯，视频，信息处理等等开发出满足行业需要并能被行业客户接受的产品这方面主要是和专业技术的结合问题，另外还有就是与专业客户的界面问题产品设计还包括专业工具类产品及民用产品，前者重点在性能，后者对价格敏感产品设计以实现产品功能为主要目的，FPGA技术是一个实现手段在这个领域，FPGA因为具备接口，控制，功能IP，内嵌CPU等特点有条件实现一个构造简单，固化程度高，功能全面的系统产品设计将是FPGA技术应用最广大的市场，具有极大的爆发性的需求空间产品设计对技术人员的要求比较高，路途也比较漫长不过现在整个行业正处在组建\"首发团队\"的状态，只要加入，前途光明产品设计是一种职业发展方向定位，不是简单的爱好就能做到的！产品设计领域会造就大量的企业和企业家，是一个近期的发展热点和机遇 3．系统级应用
系统级的应用是FPGA与传统的计算机技术结合，实现一种FPGA版的如用Xilinx V-4, V-5系列的FPGA，实现内嵌POWER PC CPU, 然后再配合各种外围功能，实现一个基本环境，在这个平台上跑LINUX等系统这个系统也就支持各种标准外设和功能接口（如图象接口）了这对于快速构成FPGA大型系统来讲是很有帮助的。这种\"山寨\"味很浓的系统早期优势不一定很明显，类似ARM系统的境况但若能慢慢发挥出FPGA的优势，逐渐实现一些特色系统也是一种发展方向。若在系统级应用中，开发人员不具备系统的扩充开发能力，只是搞搞编程是没什么意义的，当然的开发是另一种情况，搞系统级应用看似起点高，但不具备深层开发能力，很可能会变成爱好者，就如很多人会做网页但不能称做会编程类似以上是几点个人开发，希望能帮助想学FPGA但很茫然无措的人理一理思路。这是一个不错的行业，有很好的个人成功机会。但也肯定是一个竞争很激烈的行业，关键看的就是速度和深度当然还有市场适应能力。 最新应用
北京时间2010年12月30日消息，美英两国科学家联合开发了一款运算速度超快的电脑芯片，使当前台式机的运算能力提升20倍。当前的个人电脑使用双核、4核、16核处理器来执行各项任务。如今，美英研究人员开发的中央处理器(CPU)将1000个内核有效集成于一个芯片上。这项突破或将在今后几年开启一个超高速运算的新时代，使家庭用户不再对运行缓慢的电脑系统感到沮丧。虽然速度更快，但由于新型“超级”电脑的能耗远低于当前电脑，所以更加环保。
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研究人员采用了一种名为“现场可编程门阵列”(以下简称“FPGA”)的芯片，使得微晶片就像都含有数百万个晶体管一样，而晶体管则是任何电路的基本组成部分。不过，FPGA芯片可由用户安装到特定电路，它们的功能不是在出厂时就设定好的。这样一来，用户可以将晶体管划分成一个个“小群体”，要求每个“小群体”完成不同的任务。
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（本文来自：）
- 好好学习，天天向上
附录三
分频：fenpin
module fenpin(clk,clr,clk0,clk1,clk2,clk3,clk4); input clk,clr;
output clk0,clk1,clk2,clk3,clk4; reg clk0,clk1,clk2,clk3,clk4; reg[12:0] cnter0;
reg[4:0] cnter1,cnter2,cnter3,cnter4; always@(posedge clk or negedge clr) if (~clr) cnter0<=0; else
if (cnter0==4999) begin
cnter0<=0; clk0<=1'b1; end else begin
cnter0<=cnter0+1; clk0<=0; end
always@(posedge clk0 or negedge clr) if (~clr) cnter1<=0; else
if(cnter1==9) begin
cnter1<=0; clk1<=1'b1;; end
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else begin
cnter1<=cnter1+1;clk1<=0; end
always@(posedge clk1 or negedge clr) if (~clr) cnter2<=0; else
if (cnter2==9) begin
cnter2<=0; clk2<=1'b1;; end else begin
cnter2<=cnter2+1;clk2<=0; end
always@(posedge clk2 or negedge clr) if (~clr) cnter3<=0; else
if (cnter3==9) begin
cnter3<=0; clk3<=1'b1;; end else begin
cnter3<=cnter3+1;clk3<=0; end
always@(posedge clk3 or negedge clr)
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if (~clr) cnter4<=0; else
if(cnter4==9) begin
cnter4<=0; clk4<=1'b1;; end else begin
cnter4<=cnter4+1;clk4<=0; end endmodule
contr 控制端
module contr(clk,k1,k2,k); input clk,k1,k2; output k; reg[3:0] qc; reg k; reg rc;
always@(posedge clk) begin qc=qc+1; if(qc<8) rc=0; else rc=1; case ({k1,k2}) 0:k=rc; 1:k=0;
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2:k=1; 3:k=rc; endcase end endmodule
mux_4模块
module mux_4(k,jm,jf,js,jr,jy,jn,j1,j2,j3); input k,j1,j2,j3; output jm,jf,js,jr,jy,jn; reg jm,jf,js,jr,jy,jn; always begin
if(k==0) {jm,jf,js}={j1,j2,j3}; else {jr,jy,jn}={j1,j2,j3}; end endmodule
timeve模块（包括3个部分） 时
module hour(clrn,clk,qs,cout); input clrn,clk; output [7:0] qs; output cout; reg [7:0] qs; reg[3:0] qsl; reg[7:4] qsh; reg carry1;
always@(posedge clk or negedge clrn)//miao
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begin
if(~clrn) begin {qsh,qsl}=8'h00;carry1=0; end else if((qsh==2)&&(qsl==3))
begin {qsh,qsl}=8'h00; carry1=1; end else if ((qsh==2)&&(qsl<3))
begin qsh=qsh;qsl=qsl+1; carry1=0;end else if(qsl==9)
begin qsh=qsh+1;qsl=0; carry1=0 ;end else
begin qsh=qsh;qsl=qsl+1; carry1=0;end qs={qsh,qsl}; end
assign cout=carry1 ; endmodule 分
module minute(clrn,clk,jh,qf,enhour); input clrn,clk,jh; output [7:0] qf; output enhour; reg [7:0] qf; reg[3:0] qfl; reg[7:4] qfh; reg carry1;
always@(posedge clk or negedge clrn)//miao begin
if(~clrn) begin {qfh,qfl}=8'h00;carry1=0; end else if((qfh==5)&&(qfl==9))
begin {qfh,qfl}=8'h00; carry1=1; end
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else if ((qfh==5)&&(qfl<9))
begin qfh=qfh;qfl=qfl+1; carry1=0;end else if(qfl==9)
begin qfh=qfh+1;qfl=0; carry1=0 ;end else
begin qfh=qfh;qfl=qfl+1; carry1=0;end qf={qfh,qfl}; end
assign enhour=carry1|jh ; endmodule 秒
module second(clrn,clk,jf,qm,enmin); input clrn,clk,jf; output [7:0] qm; output enmin; reg [7:0] qm; reg[3:0] qml; reg[7:4] qmh; reg carry1;
always@(posedge clk or negedge clrn)//miao begin
if(~clrn) begin {qmh,qml}=0;carry1=0; end else if((qmh>=5)&&(qml>=9))
begin {qmh,qml}=0; carry1=1; end else if ((qmh==5)&&(qml<9))
begin qmh=qmh;qml=qml+1; carry1=0;end else if((qmh<5)&&(qml==9))
begin qmh=qmh+1;qml=0; carry1=0 ;end
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else if((qmh<5)&&(qml<9))
begin qmh=qmh;qml=qml+1; carry1=0;end qm={qmh,qml}; end
assign enmin=carry1 | jf ; endmodule
nyr2009
module nyr2009(clrn,clk,jn,jy,jr,qn,qy,qr); input clrn,clk,jn,jy,jr; output [15:0] qn; output [7:0] qy,qr; reg [15:0] qn; reg [7:0] qy,qr; reg clkn,clky; reg [7:0] date; reg clkn1,clkn2,clkn3;
initial begin clkn1=1;clkn2=1;clkn3=1; end initial begin qn='h2000;qy=1;qr=1; end
always@(posedge (clk^jr) or negedge clrn)//日计数 begin
if(~clrn) qr=1; else begin
if(qr==date) qr=1，clky=1;
else if(qr[7:4]==date[7:4]&&qr[3:0]==date[3:0]) qr[7:4]==qr[7:4],qr[3:0]==qr[3:0]+1,clky=0; else if(qr[7:4] -37 - 好好学习，天天向上 else if(qr[7:4] end always@(posedge (clky^jy) or negedge clrn)//月计数 begin if(~clrn) qy=1; else begin if(qy=='h12) qy=1; else qy=qy+1; if(qy[3:0]=='ha) begin qy[3:0]=0; qy[7:4]=qr[7:4]+1;end if(qy=='h12) clkn=1; else clkn=0; end end always//每月的天数 begin case(qy) 'h01:date='h31; 'h02:begin if((qn/4==0)&(qn/100!=0)|(qn/400==0)) date='h29; else date='h28;end 'h03:date='h31; 'h04:date='h30; 'h05:date='h31; 'h06:date='h30; 'h07:date='h31; 'h08:date='h31; 'h09:date='h30; 'h010:date='h31; -38 - 好好学习，天天向上 'h011:date='h30; 'h012:date='h31; default:date='h30; endcase end always@(posedge (clkn^jn) or negedge clrn) //年计数 begin if(~clrn) qn[3:0]=0; else begin if(qn[3:0]==9) qn[3:0]=0; else qn[3:0]=qn[3:0]+1; if(qn[3:0]==9) clkn1=0; else clkn1=1; end end always@(posedge (clkn1) or negedge clrn) begin if(~clrn) qn[7:4]=0; else begin if(qn[7:4]==9) qn[7:4]=0; else qn[7:4]=qn[7:4]+1; if(qn[7:4]==9) clkn2=0; else clkn2=1; end end always@(posedge (clkn2) or negedge clrn) begin if(~clrn) qn[11:8]=0; else begin if(qn[11:8]==9) qn[11:8]=0; -39 - 好好学习，天天向上 else qn[11:8]=qn[11:8]+1; if(qn[11:8]==9) clkn3=0; else clkn3=1; end end always@(posedge (clkn3) or negedge clrn) begin if(~clrn) qn[15:12]=2; else begin if(qn[15:12]==9) qn[15:12]=0; else qn[15:12]=qn[15:12]+1; end end endmodule mux_16 module mux_16(k,qm,qf,qs,qr,qy,qn,q0,q1,q2,q3,q4,q5,q6,q7); input k; input[7:0] qm,qf,qs,qr,qy; input[15:0] qn; output [3:0] q0,q1,q2,q3,q4,q5,q6,q7; reg [3:0] q0,q1,q2,q3,q4,q5,q6,q7; always begin if(k==0) begin q0=0;q1=0; q2=qs[7:4];q3=qs[3:0];q4=qf[7:4];q5=qf[3:0];q6=qm[7:4];q7=qm[3:0];end else begin q0=qn[15:12];q1=qn[11:8]; q2=qn[7:4];q3=qn[3:0];q4=qy[7:4];q5=qy[3:0];q6=qr[7:4];q7=qr[3:0];end -40 - 好好学习，天天向上 end endmodule yimaqi module yimaqi (in,out); input [3:0]in; output [6:0]out; wire [3:0] in; reg [6:0]out; always @(in) begin case(in) 4'd0:out=7'b1000000; 4'd1:out=7'b1111001; 4'd2:out=7'b0100100; 4'd3:out=7'b0110000; 4'd4:out=7'b0011001; 4'd5:out=7'b0010010; 4'd6:out=7'b0000010; 4'd7:out=7'b1111000; 4'd8:out=7'b0000000; 4'd9:out=7'b0010000; default :out=1; endcase end endmodule -41 因篇幅问题不能全部显示，请点此查看更多更全内容