RTL8305SC资料

RTL8305SC

SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES

DataSheet

Rev. 1.2 02 March 2005

Track ID: JATR-1076-21

元器件交易网www.cecb2b.com

RTL8305SC Datasheet COPYRIGHT

©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.

USING THIS DOCUMENT

This document is intended for use by the software engineer when programming for Realtek RTL8305SC controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document.

Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller ii Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet REVISION HISTORY

Revision Release Date Summary 1.0 2004/06/17 First release. 1.1 2004/06/30 Removed QoS function IPv6 differentiated services and removed Table 147, page 113.

Revised LEDMODE[1:0]=00, in Table 4, page 14, Table 7, page 20, Table 19, page 30, and Table 69, page 59.

Changed four combinations of LED mode to three combinations of LED display mode, page 3.

1.2 2005/03/02 Corrected section 7.3.10 PHY 2 Register 23: “Port 2 Control Register 1” to “Global Option 1

Register”, page 71.

Revised pull low resister to 1k ohm, Table 5, page 16. Revised PHY register in Table 64, page 55.

Changed Table 139’s name from PHY 0 to PHY 5, page 87. Changed Table 140’s name from PHY 8 to PHY 5, page 88. Add P4PHY_MODE select, in Table 143, page 103.

Corrected Pin52 MTXEN/PRXDV/EN_TRUNK to MTXEN/PRXDV, Pin92

LED_ACT[4]/DISFCAUTOOFF to LED_ACT[4], and Pin115 ENAGBACK/LED_DUP[0] to LED_DUP[0], in Figure 2, page 7, and Table 1, page 8.

Canceled the description of Pin92 LED_ACT[4]/DISFCAUTOOFF and Pin115

ENAGBACK/LED_DUP[0], section 1, page 2, in Table 9, page 22, and section 8.3.10, page 123.

Reserved PHY 0 Register 18.7 and 18.15, in Table 68, page 58.

Reserved EEPROM Register 4.7, in Table 16, page 28 and Register 5.7, Table 17, page 29. Corrected QoS based features, section 2, page 4.

Corrected 2SB1188K to 2SB1188 and HVDD18 to DVDD18, in Figure 24, page 132, and Table 151, page 132.

Corrected “24LC02 must be 1.8Vcompatible” to “24LC02 must be 3.3Vcompatible”, section 8.3.3, page 117.

Corrected TTL Input High Voltage 1.5V to 2.0V and TTL Input Low Voltage 1.0V to 0.8V, section 9.3, page 134.

Corrected PHY 4 register 18 description, in Table 124, page 81.

Add 100Base-TX TD and RD Differential Output Impedance (return loss) columns and delete 10Base-TX TD and RD Differential Output Impedance (return loss) columns, in Section 9.4 AC Characteristics, page 135.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller iii Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Table of Contents

1. GENERAL DESCRIPTION................................................................................................................................................1 2. FEATURES...........................................................................................................................................................................4 3. BLOCK DIAGRAM.............................................................................................................................................................6 4. PIN ASSIGNMENTS...........................................................................................................................................................7 5. PIN DESCRIPTIONS..........................................................................................................................................................9 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10.

MEDIA CONNECTION PINS............................................................................................................................................9 PORT 4 CONFIGURATION PINS......................................................................................................................................9 PORT 4 MAC CIRCUIT INTERFACE PINS.....................................................................................................................14 PORT 4 PHY CIRCUIT INTERFACE PINS......................................................................................................................16 MISCELLANEOUS PINS...............................................................................................................................................19 PORT LED PINS.........................................................................................................................................................20 SERIAL EEPROM AND SMI PINS..............................................................................................................................22 STRAPPING PINS.........................................................................................................................................................22 PORT STATUS STRAPPING PINS...................................................................................................................................24 POWER PINS...............................................................................................................................................................26

6. EEPROM DESCRIPTION................................................................................................................................................27 6.1. PORT 0 REGISTERS.....................................................................................................................................................27 6.1.1. Global Control Register0.....................................................................................................................................27 6.1.2. Global Control Register1.....................................................................................................................................27 6.1.3. Global Control Register2.....................................................................................................................................28 6.1.4. Global Control Register3.....................................................................................................................................28 6.1.5. Global Control Register4.....................................................................................................................................28 6.1.6. Global Control Register5.....................................................................................................................................29 6.1.7. Global Control Register6.....................................................................................................................................29 6.1.8. Global Control Register7.....................................................................................................................................30 6.1.9. Port 0 Control 0....................................................................................................................................................30 6.1.10. Port 0 Control 1....................................................................................................................................................31 6.1.11. Port 0 Control 2....................................................................................................................................................31 6.1.12. Port 0 Control 3....................................................................................................................................................31 6.1.13. Port 0 Control 4 & VLAN Entry [A].....................................................................................................................32 6.2. PORT 1 REGISTERS.....................................................................................................................................................33 6.2.1. Internal Use Register............................................................................................................................................33 6.2.2. Port 1 Control 0....................................................................................................................................................33 6.2.3. Port 1 Control 1....................................................................................................................................................34 6.2.4. Port 1 Control 2....................................................................................................................................................34 6.2.5. Port 1 Control 3....................................................................................................................................................34 6.2.6. Port 1 Control 4 & VLAN Entry [B].....................................................................................................................35 6.3. PORT 2 REGISTERS.....................................................................................................................................................36 6.3.1. Internal Use Register............................................................................................................................................36 6.3.2. Port 2 Control 0....................................................................................................................................................36 6.3.3. Port 2 Control 1....................................................................................................................................................37 6.3.4. Reserved...............................................................................................................................................................37 6.3.5. Port 2 Control 2 & VLAN Entry [C]....................................................................................................................38 6.4. PORT 3 REGISTERS.....................................................................................................................................................39 6.4.1. Switch MAC Address............................................................................................................................................39 6.4.2. Port 3 Control 0....................................................................................................................................................39 6.4.3. Port 3 Control 1....................................................................................................................................................40 6.4.4. Reserved...............................................................................................................................................................40

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

iv Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 6.4.5. Port 3 Control 2 & VLAN Entry [D]....................................................................................................................40 6.4.6. Internal Use Register............................................................................................................................................41 6.5. PORT 4 REGISTERS.....................................................................................................................................................42 6.5.1. Port 4 Control 0....................................................................................................................................................42 6.5.2. Port 4 Control 1....................................................................................................................................................42 6.5.3. Reserved...............................................................................................................................................................43 6.5.4. Port 4 Control 2 & VLAN Entry [E].....................................................................................................................43 6.5.5. Internal Use Register............................................................................................................................................44 6.5.6. 802.1p Base Priority.............................................................................................................................................44 6.6. VLAN ENTRIES.........................................................................................................................................................44 6.6.1. VLAN Entry [F]....................................................................................................................................................44 6.6.2. VLAN Entry [G]...................................................................................................................................................45 6.6.3. VLAN Entry [H]...................................................................................................................................................45 6.6.4. VLAN Entry [I].....................................................................................................................................................46 6.6.5. VLAN Entry [J]....................................................................................................................................................46 6.6.6. VLAN Entry [K]....................................................................................................................................................47 6.6.7. VLAN Entry [L]....................................................................................................................................................47 6.6.8. VLAN Entry [M]...................................................................................................................................................48 6.6.9. VLAN Entry [N]....................................................................................................................................................48 6.6.10. VLAN Entry [O]...................................................................................................................................................49 6.6.11. VLAN Entry [P]....................................................................................................................................................49 7. REGISTER DESCRIPTIONS..........................................................................................................................................50 7.1. PHY 0 REGISTERS.....................................................................................................................................................53 7.1.1. PHY 0 Register 0 for Port 0: Control...................................................................................................................53 7.1.2. PHY 0 Register 1 for Port 0: Status......................................................................................................................54 7.1.3. PHY 0 Register 2 for Port 0: PHY Identifier 1.....................................................................................................54 7.1.4. PHY 0 Register 3 for Port 0: PHY Identifier 2.....................................................................................................55 7.1.5. PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement............................................................................55 7.1.6. PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability...................................................................56 7.1.7. PHY 0 Register 16: Global Control 0...................................................................................................................56 7.1.8. PHY 0 Register 17: Global Control 1...................................................................................................................58 7.1.9. PHY 0 Register 18: Global Control 2...................................................................................................................58 7.1.10. PHY 0 Register 19: Global Control 3...................................................................................................................59 7.1.11. PHY 0 Register 22: Port 0 Control Register 0......................................................................................................60 7.1.12. PHY 0 Register 24: Port 0 Control Register 1 & VLAN ID [A] Membership......................................................61 7.1.13. PHY 0 Register 25: Port 0 Control Register 2 & VLAN ID [A]...........................................................................61 7.1.14. PHY 0 Register 26: Reserved or VLAN ID [F] Membership................................................................................62 7.1.15. PHY 0 Register 27: Reserved or VLAN ID [F].....................................................................................................62 7.1.16. PHY 0 Register 28: Reserved or VLAN ID [K] Membership................................................................................63 7.1.17. PHY 0 Register 29: Reserved or VLAN ID [K]....................................................................................................63 7.1.18. PHY 0 Register 30: Reserved or VLAN ID [P] Membership................................................................................64 7.1.19. PHY 0 Register 31: Reserved or VLAN ID [P].....................................................................................................64 7.2. PHY 1 REGISTERS.....................................................................................................................................................65 7.2.1. PHY 1 Register 0 for Port 1: Control...................................................................................................................65 7.2.2. PHY 1 Register 1 for Port 1: Status......................................................................................................................65 7.2.3. PHY 1 Register 2 for Port 1: PHY Identifier 1.....................................................................................................65 7.2.4. PHY 1 Register 3 for Port 1: PHY Identifier 2.....................................................................................................65 7.2.5. PHY 1 Register 4 for Port 1: Auto-Negotiation Advertisement............................................................................65 7.2.6. PHY 1 Register 5 for Port 1: Auto-Negotiation Link Partner Ability...................................................................65 7.2.7. PHY 1 Register 16~17: Internal Use Register......................................................................................................65 7.2.8. PHY 1 Register 18~19: Internal Use Register......................................................................................................65 7.2.9. PHY 1 Register 22: Port 1 Control Register 0......................................................................................................66 7.2.10. PHY 1 Register 23: Global Option Register 0......................................................................................................66 7.2.11. PHY 1 Register 24: Port 1 Control Register 1 & VLAN ID [B] Membership......................................................66

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

v Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.2.12. PHY 1 Register 25: Port 1 Control Register 2 & VLAN ID [B]...........................................................................67 7.2.13. PHY 1 Register 26: Reserved or VLAN ID [G] Membership...............................................................................67 7.2.14. PHY 1 Register 27: Reserved or VLAN ID [G]....................................................................................................68 7.2.15. PHY 1 Register 28: Reserved or VLAN ID [L] Membership................................................................................68 7.2.16. PHY 1 Register 29: Reserved or VLAN ID [L].....................................................................................................69 7.3. PHY 2 REGISTERS.....................................................................................................................................................70 7.3.1. PHY 2 Register 0 for Port 2: Control...................................................................................................................70 7.3.2. PHY 2 Register 1 for Port 2: Status......................................................................................................................70 7.3.3. PHY 2 Register 2 for Port 2: PHY Identifier 1.....................................................................................................70 7.3.4. PHY 2 Register 3 for Port 2: PHY Identifier 2.....................................................................................................70 7.3.5. PHY 2 Register 4 for Port 2: Auto-Negotiation Advertisement............................................................................70 7.3.6. PHY 2 Register 5 for Port 2: Auto-Negotiation Link Partner Ability...................................................................70 7.3.7. PHY 2 Register 16~17: Internal Use Register......................................................................................................70 7.3.8. PHY 2 Register 18~19: Internal Use Register......................................................................................................70 7.3.9. PHY 2 Register 22: Port 2 Control Register 0......................................................................................................71 7.3.10. PHY 2 Register 23: Global Option 1 Register......................................................................................................71 7.3.11. PHY 2 Register 24: Port 2 Control Register 2 & VLAN ID [C] Membership......................................................71 7.3.12. PHY 2 Register 25: Port 2 Control Register 3 & VLAN ID [C]...........................................................................72 7.3.13. PHY 2 Register 26: Reserved or VLAN ID [H] Membership...............................................................................72 7.3.14. PHY 2 Register 27: Reserved or VLAN ID [H]....................................................................................................73 7.3.15. PHY 2 Register 28: Reserved or VLAN ID [M] Membership...............................................................................73 7.3.16. PHY 2 Register 29: Reserved or VLAN ID [M]....................................................................................................74 7.4. PHY 3 REGISTERS.....................................................................................................................................................75 7.4.1. PHY 3 Register 0 for Port 3: Control...................................................................................................................75 7.4.2. PHY 3 Register 1 for Port 3: Status......................................................................................................................75 7.4.3. PHY 3 Register 2 for Port 3: PHY Identifier 1.....................................................................................................75 7.4.4. PHY 3 Register 3 for Port 3: PHY Identifier 2.....................................................................................................75 7.4.5. PHY 3 Register 4 for Port 3: Auto-Negotiation Advertisement............................................................................75 7.4.6. PHY 3 Register 5 for Port 3: Auto-Negotiation Link Partner Ability...................................................................75 7.4.7. PHY 3 Register 16~18: Switch MAC Address......................................................................................................75 7.4.8. PHY 3 Register 19~21: Internal Use Register......................................................................................................76 7.4.9. PHY 3 Register 22: Port 3 Control Register 0......................................................................................................76 7.4.10. PHY 3 Register 24: Port 3 Control Register 1 & VLAN ID [D] Membership......................................................76 7.4.11. PHY 3 Register 25: Port 3 Control Register 2 & VLAN ID [D]...........................................................................77 7.4.12. PHY 3 Register 26: Reserved or VLAN ID [I] Membership.................................................................................77 7.4.13. PHY 3 Register 27: Reserved or VLAN ID [I]......................................................................................................78 7.4.14. PHY 3 Register 28: Reserved or VLAN ID [N] Membership................................................................................78 7.4.15. PHY 3 Register 29: Reserved or VLAN ID [N]....................................................................................................79 7.5. PHY 4 REGISTERS.....................................................................................................................................................80 7.5.1. PHY 4 Register 0 for Port 4: Control...................................................................................................................80 7.5.2. PHY 4 Register 1 for Port 4: Status......................................................................................................................80 7.5.3. PHY 4 Register 2 for Port 4: PHY Identifier 1.....................................................................................................80 7.5.4. PHY 4 Register 3 for Port 4: PHY Identifier 2.....................................................................................................80 7.5.5. PHY 4 Register 4 for Port 4: Auto-Negotiation Advertisement............................................................................80 7.5.6. PHY 4 Register 5 for Port 4: Auto-Negotiation Link Partner Ability...................................................................80 7.5.7. PHY 4 Register 16: Indirect Access Control.........................................................................................................80 7.5.8. PHY 4 Register 17~20: Indirect Access Data.......................................................................................................81 7.5.9. PHY 4 Register 21: 802.1p Base Priority.............................................................................................................81 7.5.10. PHY 4 Register 22: Port 4 Control Register 0......................................................................................................82 7.5.11. PHY 4 Register 24: Port 4 Control Register 1 & VLAN ID [E] Membership......................................................82 7.5.12. PHY 4 Register 25: Port 4 Control Register 2 & VLAN ID [E]...........................................................................83 7.5.13. PHY 4 Register 26: Reserved or VLAN ID [J] Membership................................................................................83 7.5.14. PHY 4 Register 27: Reserved or VLAN ID [J].....................................................................................................84 7.5.15. PHY 4 Register 28: Reserved or VLAN ID [O] Membership...............................................................................84 7.5.16. PHY 4 Register 29: Reserved or VLAN ID [O]....................................................................................................85

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

vi Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.6. PHY 5 REGISTERS.....................................................................................................................................................86 7.6.1. PHY 5 Register 0 for Port 4 MAC: Control..........................................................................................................86 7.6.2. PHY 5 Register 1 for Port 4 MAC: Status............................................................................................................87 7.6.3. PHY 5 Register 2 for Port 4 MAC: PHY Identifier 1............................................................................................87 7.6.4. PHY 5 Register 3 for Port 4 MAC: PHY Identifier 2............................................................................................87 7.6.5. PHY 5 Register 4 for Port 4 MAC: Auto-Negotiation Advertisement...................................................................88 7.6.6. MII Port NWay Mode...........................................................................................................................................89 7.6.7. MII Port Force Mode...........................................................................................................................................89 8. FUNCTIONAL DESCRIPTION.......................................................................................................................................90 8.1. SWITCH CORE FUNCTIONAL OVERVIEW.....................................................................................................................90 8.1.1. Applications..........................................................................................................................................................90 8.1.2. Port 4....................................................................................................................................................................90 8.1.3. Port Status Configuration.....................................................................................................................................94 8.1.4. Flow Control........................................................................................................................................................95 8.1.5. Address Search, Learning, and Aging..................................................................................................................97 8.1.6. Address Direct Mapping Mode.............................................................................................................................97 8.1.7. Half Duplex Operation.........................................................................................................................................98 8.1.8. InterFrame Gap....................................................................................................................................................98 8.1.9. Illegal Frame........................................................................................................................................................98 8.1.10. Dual MII Interface................................................................................................................................................99 8.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW..............................................................................................................110 8.2.1. Auto-Negotiation for UTP..................................................................................................................................110 8.2.2. 10Base-T Transmit Function..............................................................................................................................110 8.2.3. 10Base-T Receive Function................................................................................................................................111 8.2.4. Link Monitor.......................................................................................................................................................111 8.2.5. 100Base-TX Transmit Function..........................................................................................................................111 8.2.6. 100Base-TX Receive Function............................................................................................................................111 8.2.7. 100Base-FX........................................................................................................................................................111 8.2.8. 100Base-FX Transmit Function..........................................................................................................................112 8.2.9. 100Base-FX Receive Function...........................................................................................................................112 8.2.10. 100Base-FX FEFI..............................................................................................................................................112 8.2.11. Reduced Fiber Interface.....................................................................................................................................113 8.2.12. Power Saving Mode............................................................................................................................................113 8.2.13. Reg0.11 Power-Down Mode...............................................................................................................................114 8.2.14. Crossover Detection and Auto Correction..........................................................................................................114 8.2.15. Polarity Detection and Correction.....................................................................................................................114 8.3. ADVANCED FUNCTIONAL OVERVIEW.......................................................................................................................115 8.3.1. Reset...................................................................................................................................................................115 8.3.2. Setup and Configuration.....................................................................................................................................116 8.3.3. Serial EEPROM Example: 24LC02....................................................................................................................117 8.3.4. SMI.....................................................................................................................................................................119 8.3.5. Head-Of-Line Blocking......................................................................................................................................119 8.3.6. Port-Based VLAN...............................................................................................................................................119 8.3.7. IEEE 802.1Q Tagged-VID Based VLAN.............................................................................................................121 8.3.8. Port VID (PVID).................................................................................................................................................122 8.3.9. Lookup Table Access...........................................................................................................................................123 8.3.10. QoS Function......................................................................................................................................................123 8.3.11. Insert/Remove VLAN Tag....................................................................................................................................125 8.3.12. Filtering/Forwarding Reserved Control Frame.................................................................................................125 8.3.13. Broadcast Storm Control....................................................................................................................................126 8.3.14. Broadcast In/Out Drop.......................................................................................................................................126 8.3.15. Loop Detection...................................................................................................................................................127 8.3.16. MAC Local Loopback Return to External..........................................................................................................128 8.3.17. Reg.0.14 PHY Digital Loopback Return to Internal...........................................................................................129

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

vii Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 8.3.18. LEDs...................................................................................................................................................................129 8.3.19. 1.8V Power Generation......................................................................................................................................132 8.3.20. Crystal/Oscillator...............................................................................................................................................132 9. CHARACTERISTICS.....................................................................................................................................................133 9.1. ABSOLUTE MAXIMUM RATINGS...............................................................................................................................133 9.2. OPERATING RANGE..................................................................................................................................................133 9.3. DC CHARACTERISTICS.............................................................................................................................................134 9.4. AC CHARACTERISTICS.............................................................................................................................................135 9.5. DIGITAL TIMING CHARACTERISTICS.........................................................................................................................136 9.6. THERMAL CHARACTERISTICS...................................................................................................................................139 9.6.1. Package Description..........................................................................................................................................139 9.6.2. PCB Description.................................................................................................................................................139 9.6.3. Assembly Material..............................................................................................................................................139 9.6.4. Simulation Analysis Conditions..........................................................................................................................140 9.6.5. Results................................................................................................................................................................140 10.

APPLICATION INFORMATION..............................................................................................................................141 UTP (10BASE-T/100BASE-TX) APPLICATION.........................................................................................................141 100BASE-FX APPLICATION......................................................................................................................................143

10.1. 10.2. 11. 12. 13.

DESIGN AND LAYOUT GUIDE................................................................................................................................145 MECHANICAL DIMENSIONS.................................................................................................................................147 MECHANICAL DIMENSIONS NOTES..........................................................................................................................148 ORDERING INFORMATION....................................................................................................................................148

12.1.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller viii Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet List of Tables

TABLE 1. PIN ASSIGNMENTS..........................................................................................................................................................8 TABLE 2. MEDIA CONNECTION PINS.............................................................................................................................................9 TABLE 3. PORT 4 CONFIGURATION PIN DEFINITIONS.....................................................................................................................9 TABLE 4. PORT 4 MAC CIRCUIT INTERFACE PIN DEFINITIONS...................................................................................................14 TABLE 5. PORT 4 PHY CIRCUIT INTERFACE PIN DEFINITIONS.....................................................................................................16 TABLE 6. MISCELLANEOUS PINS.................................................................................................................................................19 TABLE 7. PORT LED PINS...........................................................................................................................................................20 TABLE 8. SERIAL EEPROM AND SMI PINS................................................................................................................................22 TABLE 9. STRAPPING PINS...........................................................................................................................................................22 TABLE 10. PORT STATUS STRAPPING PINS.....................................................................................................................................24 TABLE 11. POWER PINS.................................................................................................................................................................26 TABLE 12. GLOBAL CONTROL REGISTER0....................................................................................................................................27 TABLE 13. GLOBAL CONTROL REGISTER1....................................................................................................................................27 TABLE 14. GLOBAL CONTROL REGISTER2....................................................................................................................................28 TABLE 15. GLOBAL CONTROL REGISTER3....................................................................................................................................28 TABLE 16. GLOBAL CONTROL REGISTER4....................................................................................................................................28 TABLE 17. GLOBAL CONTROL REGISTER5....................................................................................................................................29 TABLE 18. GLOBAL CONTROL REGISTER6....................................................................................................................................29 TABLE 19. GLOBAL CONTROL REGISTER 7....................................................................................................................................30 TABLE 20. PORT 0 CONTROL 0......................................................................................................................................................30 TABLE 21. PORT 0 CONTROL 1......................................................................................................................................................31 TABLE 22. PORT 0 CONTROL 2......................................................................................................................................................31 TABLE 23. PORT 0 CONTROL 3......................................................................................................................................................31 TABLE 24. PORT 0 CONTROL 4 & VLAN ENTRY [A]....................................................................................................................32 TABLE 25. INTERNAL USE REGISTER.............................................................................................................................................33 TABLE 26. PORT 1 CONTROL 0......................................................................................................................................................33 TABLE 27. PORT 1 CONTROL 1......................................................................................................................................................34 TABLE 28. PORT 1 CONTROL 2......................................................................................................................................................34 TABLE 29. PORT 1 CONTROL 2......................................................................................................................................................34 TABLE 30. PORT 1 CONTROL 4 & VLAN ENTRY [B]....................................................................................................................35 TABLE 31. INTERNAL USE REGISTER.............................................................................................................................................36 TABLE 32. PORT 2 CONTROL 0......................................................................................................................................................36 TABLE 33. PORT 2 CONTROL 1......................................................................................................................................................37 TABLE 34. RESERVED....................................................................................................................................................................37 TABLE 35. PORT 2 CONTROL 2 & VLAN ENTRY [C]....................................................................................................................38 TABLE 36. SWITCH MAC ADDRESS..............................................................................................................................................39 TABLE 37. PORT 3 CONTROL 0......................................................................................................................................................39 TABLE 38. PORT 3 CONTROL 1......................................................................................................................................................40 TABLE 39. RESERVED....................................................................................................................................................................40 TABLE 40. PORT 3 CONTROL 2 & VLAN ENTRY [D]....................................................................................................................40 TABLE 41. INTERNAL USE REGISTER.............................................................................................................................................41 TABLE 42. PORT 4 CONTROL 0......................................................................................................................................................42 TABLE 43. PORT 4 CONTROL 1......................................................................................................................................................42 TABLE 44. RESERVED....................................................................................................................................................................43 TABLE 45. PORT 4 CONTROL 2 & VLAN ENTRY [E].....................................................................................................................43 TABLE 46. INTERNAL USE REGISTER.............................................................................................................................................44 TABLE 47. 802.1P BASE PRIORITY.................................................................................................................................................44 TABLE 48. VLAN ENTRY [F]........................................................................................................................................................44 TABLE 49. VLAN ENTRY [G].......................................................................................................................................................45 TABLE 50. VLAN ENTRY [H].......................................................................................................................................................45 TABLE 51. VLAN ENTRY [I].........................................................................................................................................................46 TABLE 52. VLAN ENTRY [J].........................................................................................................................................................46

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

ix Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet TABLE 53. VLAN ENTRY [K].......................................................................................................................................................47 TABLE 54. VLAN ENTRY [L]........................................................................................................................................................47 TABLE 55. VLAN ENTRY [M].......................................................................................................................................................48 TABLE 56. VLAN ENTRY [N].......................................................................................................................................................48 TABLE 57. VLAN ENTRY [O].......................................................................................................................................................49 TABLE 58. VLAN ENTRY [P]........................................................................................................................................................49 TABLE 59. REGISTER DESCRIPTIONS.............................................................................................................................................50 TABLE 60. PHY 0 REGISTER 0: CONTROL.....................................................................................................................................53 TABLE 61. PHY 0 REGISTER 1: STATUS........................................................................................................................................54 TABLE 62. PHY 0 REGISTER 2: PHY IDENTIFIER 1.......................................................................................................................54 TABLE 63. PHY 0 REGISTER 3: PHY IDENTIFIER 2.......................................................................................................................55 TABLE 64. PHY 0 REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT........................................................................................55 TABLE 65. PHY 0 REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY..............................................................................56 TABLE 66. PHY 0 REGISTER 16: GLOBAL CONTROL 0..................................................................................................................56 TABLE 67. PHY 0 REGISTER 17: GLOBAL CONTROL 1..................................................................................................................58 TABLE 68. PHY 0 REGISTER 18: GLOBAL CONTROL 2..................................................................................................................58 TABLE 69. PHY 0 REGISTER 19: GLOBAL CONTROL 3..................................................................................................................59 TABLE 70. PHY 0 REGISTER 22: PORT 0 CONTROL REGISTER 0...................................................................................................60 TABLE 71. PHY 0 REGISTER 24: PORT 0 CONTROL REGISTER 1 & VLAN ID [A] MEMBERSHIP.................................................61 TABLE 72. PHY 0 REGISTER 25: PORT 0 REGISTER CONTROL 2 & VLAN ID [A]........................................................................61 TABLE 73. PHY 0 REGISTER 26: RESERVED REGISTER.................................................................................................................62 TABLE 74. PHY 0 REGISTER 26: VLAN ID [F] MEMBERSHIP......................................................................................................62 TABLE 75. PHY 0 REGISTER 27: RESERVED REGISTER.................................................................................................................62 TABLE 76. PHY 0 REGISTER 27: VLAN ID [F]............................................................................................................................62 TABLE 77. PHY 0 REGISTER 28: RESERVED REGISTER.................................................................................................................63 TABLE 78. PHY 0 REGISTER 28: VLAN ID [K] MEMBERSHIP.....................................................................................................63 TABLE 79. PHY 0 REGISTER 29: RESERVED REGISTER.................................................................................................................63 TABLE 80. PHY 0 REGISTER 29: VLAN ID [K]............................................................................................................................63 TABLE 81. PHY 0 REGISTER 30: RESERVED REGISTER.................................................................................................................64 TABLE 82. PHY 0 REGISTER 30: VLAN ID [P] MEMBERSHIP......................................................................................................64 TABLE 83. PHY 0 REGISTER 31: RESERVED REGISTER.................................................................................................................64 TABLE 84. PHY 0 REGISTER 31: VLAN ID [P]............................................................................................................................64 TABLE 85. PHY 1 REGISTER 16~17: INTERNAL USE REGISTER....................................................................................................65 TABLE 86. PHY 1 REGISTER 18~19: INTERNAL USE REGISTER....................................................................................................65 TABLE 87. PHY 1 REGISTER 23: GLOBAL OPTION REGISTER 0.....................................................................................................66 TABLE 88. PHY 1 REGISTER 24: PORT 1 CONTROL REGISTER 1 & VLAN ID [B] MEMBERSHIP..................................................66 TABLE 89. PHY 1 REGISTER 25: PORT 1 CONTROL REGISTER 2 & VLAN ENTRY [B]..................................................................67 TABLE 90. PHY 1 REGISTER 26: RESERVED REGISTER.................................................................................................................67 TABLE 91. PHY 1 REGISTER 26: VLAN ID [G] MEMBERSHIP.....................................................................................................67 TABLE 92. PHY 1 REGISTER 27: RESERVED REGISTER.................................................................................................................68 TABLE 93. PHY 1 REGISTER 27: VLAN ID [G]............................................................................................................................68 TABLE 94. PHY 1 REGISTER 28: RESERVED REGISTER.................................................................................................................68 TABLE 95. PHY 1 REGISTER 28: VLAN ID [L] MEMBERSHIP......................................................................................................68 TABLE 96. PHY 1 REGISTER 29: RESERVED REGISTER.................................................................................................................69 TABLE 97. PHY 1 REGISTER 29: VLAN ID [L]............................................................................................................................69 TABLE 98. PHY 2 REGISTER 16~17: INTERNAL USE REGISTER....................................................................................................70 TABLE 99. PHY 2 REGISTER 18~19: INTERNAL USE REGISTER....................................................................................................70 TABLE 100. PHY 2 REGISTER 23: GLOBAL OPTION REGISTER 1...................................................................................................71 TABLE 101. PHY 2 REGISTER 24: PORT 2 CONTROL REGISTER 2 & VLAN ID [C] MEMBERSHIP................................................71 TABLE 102. PHY 2 REGISTER 25: PORT 2 CONTROL REGISTER 3 & VLAN ID [C]......................................................................72 TABLE 103. PHY 2 REGISTER 26: RESERVED REGISTER...............................................................................................................72 TABLE 104. PHY 2 REGISTER 26: VLAN ID [H] MEMBERSHIP...................................................................................................72 TABLE 105. PHY 2 REGISTER 27: RESERVED REGISTER...............................................................................................................73 TABLE 106. PHY 2 REGISTER 27: VLAN ID [H]..........................................................................................................................73 TABLE 107. PHY 2 REGISTER 28: RESERVED REGISTER...............................................................................................................73

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet TABLE 108. PHY 2 REGISTER 28: VLAN ID [M] MEMBERSHIP...................................................................................................73 TABLE 109. PHY 2 REGISTER 29: RESERVED REGISTER...............................................................................................................74 TABLE 110. PHY 2 REGISTER 29: VLAN ID [M].........................................................................................................................74 TABLE 111. PHY 3 REGISTER 16~18: SWITCH MAC ADDRESS....................................................................................................75 TABLE 112. PHY 3 REGISTER 19~21: INTERNAL USE REGISTER..................................................................................................76 TABLE 113. PHY 3 REGISTER 24: PORT 3 CONTROL REGISTER 1 & VLAN ID [D] MEMBERSHIP................................................76 TABLE 114. PHY 3 REGISTER 25: PORT 3 CONTROL REGISTER 2 & VLAN ID [D]......................................................................77 TABLE 115. PHY 3 REGISTER 26: RESERVED REGISTER...............................................................................................................77 TABLE 116. PHY 3 REGISTER 26: VLAN ID [I] MEMBERSHIP.....................................................................................................77 TABLE 117. PHY 3 REGISTER 27: RESERVED REGISTER...............................................................................................................78 TABLE 118. PHY 3 REGISTER 27: VLAN ID [I]...........................................................................................................................78 TABLE 119. PHY 3 REGISTER 28: RESERVED REGISTER...............................................................................................................78 TABLE 120. PHY 3 REGISTER 28: VLAN ID [N] MEMBERSHIP...................................................................................................78 TABLE 121. PHY 3 REGISTER 29: RESERVED REGISTER...............................................................................................................79 TABLE 122. PHY 3 REGISTER 29: VLAN ID [N]..........................................................................................................................79 TABLE 123. PHY 4 REGISTER 16: INDIRECT ACCESS CONTROL....................................................................................................80 TABLE 124. PHY 4 REGISTER 17~20: INDIRECT ACCESS DATA....................................................................................................81 TABLE 125. PHY 2 REGISTER 20: 802.1P BASE PRIORITY............................................................................................................81 TABLE 126. PHY 4 REGISTER 24: PORT 4 CONTROL REGISTER 1 & VLAN ID [E] MEMBERSHIP................................................82 TABLE 127. PHY 4 REGISTER 25: PORT 4 CONTROL REGISTER 2 & VLAN ID [E]......................................................................83 TABLE 128. PHY 4 REGISTER 26: RESERVED REGISTER...............................................................................................................83 TABLE 129. PHY 4 REGISTER 26: VLAN ID [J] MEMBERSHIP.....................................................................................................83 TABLE 130. PHY 4 REGISTER 27: RESERVED REGISTER...............................................................................................................84 TABLE 131. PHY 4 REGISTER 27: VLAN ID [J]...........................................................................................................................84 TABLE 132. PHY 4 REGISTER 28: RESERVED REGISTER...............................................................................................................84 TABLE 133. PHY 4 REGISTER 28: VLAN ID [O] MEMBERSHIP...................................................................................................84 TABLE 134. PHY 4 REGISTER 29: RESERVED REGISTER...............................................................................................................85 TABLE 135. PHY 4 REGISTER 29: VLAN ID [O]..........................................................................................................................85 TABLE 136. PHY 5 REGISTER 0: CONTROL...................................................................................................................................86 TABLE 137. PHY 5 REGISTER 1: STATUS......................................................................................................................................87 TABLE 138. PHY 5 REGISTER 2: PHY IDENTIFIER 1.....................................................................................................................87 TABLE 139. PHY 5 REGISTER 3: PHY IDENTIFIER 2.....................................................................................................................87 TABLE 140. PHY 5 REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT......................................................................................88 TABLE 141. MII PORT NWAY MODE.............................................................................................................................................89 TABLE 142. MII PORT FORCE MODE.............................................................................................................................................89 TABLE 143. MII REGISTER DEFINITION FOR PHY 4 AND PHY 5.................................................................................................103 TABLE 144. PECL DC CHARACTERISTICS..................................................................................................................................112 TABLE 145. SMI READ/WRITE CYCLES......................................................................................................................................119 TABLE 146. 802.1Q VLAN TAG FRAME FORMAT.......................................................................................................................124 TABLE 147. IPV4 FRAME FORMAT..............................................................................................................................................124 TABLE 148. RESERVED MULTICAST ADDRESS.............................................................................................................................125 TABLE 149. LOOP FRAME FORMAT..............................................................................................................................................127 TABLE 150. SPD AND BI-COLOR LINK/ACT TRUTH TABLE..........................................................................................................130 TABLE 151. AN EXAMPLE USING POWER TRANSISTOR 2SB1188................................................................................................132 TABLE 152. ELECTRICAL CHARACTERISTICS/RATINGS...............................................................................................................133 TABLE 153. LED TIMING............................................................................................................................................................136 TABLE 154. MII & SMI DC TIMING...........................................................................................................................................137 TABLE 155. PACKAGE DESCRIPTION...........................................................................................................................................139 TABLE 156. PCB DESCRIPTION...................................................................................................................................................139 TABLE 157. ASSEMBLY MATERIAL..............................................................................................................................................139 TABLE 158. SIMULATION ANALYSIS CONDITIONS.......................................................................................................................140 TABLE 159. RESULTS...................................................................................................................................................................140 TABLE 160. TRANSFORMER VENDORS........................................................................................................................................141 TABLE 161. ORDERING INFORMATION.........................................................................................................................................148

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RTL8305SC Datasheet List of Figures

FIGURE 1. BLOCK DIAGRAM.........................................................................................................................................................6 FIGURE 2. PIN ASSIGNMENTS........................................................................................................................................................7 FIGURE 3. PORT 4 OPERATING MODE OVERVIEW........................................................................................................................93 FIGURE 4. TRADITIONAL APPLICATION........................................................................................................................................99 FIGURE 5. DUAL MII APPLICATION DIAGRAM..........................................................................................................................100 FIGURE 6. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT............101 FIGURE 7. DUAL MII MODE WITH 1 MII-MAC + 1 MII-PHY (100BASE-FX MODE) INTERFACES APPLICATION CIRCUIT.......101 FIGURE 8. DUAL MII MODE WITH 1 MII-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT.............102 FIGURE 9. DUAL MII MODE WITH 1 SNI-PHY + 1 MII-PHY (100BASE-T UTP) INTERFACES APPLICATION CIRCUIT.............102 FIGURE 10. RESET.......................................................................................................................................................................115 FIGURE 11. START AND STOP DEFINITION...................................................................................................................................117 FIGURE 12. OUTPUT ACKNOWLEDGE..........................................................................................................................................117 FIGURE 13. RANDOM READ........................................................................................................................................................118 FIGURE 14. SEQUENTIAL READ...................................................................................................................................................118 FIGURE 15. VLAN GROUPING EXAMPLE....................................................................................................................................120 FIGURE 16. TAGGED AND UNTAGGED PACKET FORWARDING WHEN 802.1Q TAG AWARE VLAN IS DISABLED...........................122 FIGURE 17. INPUT DROP VS. OUTPUT DROP................................................................................................................................126 FIGURE 18. LOOP EXAMPLE........................................................................................................................................................127 FIGURE 19. PORT 4 LOOPBACK...................................................................................................................................................128 FIGURE 20. REG. 0.14 LOOPBACK...............................................................................................................................................129 FIGURE 21. FLOATING AND PULL-DOWN OF LED PINS...............................................................................................................130 FIGURE 22. TWO PIN BI-COLOR LED FOR SPD FLOATING OR PULL-HIGH..................................................................................131 FIGURE 23. TWO PIN BI-COLOR LED FOR SPD PULL-DOWN......................................................................................................131 FIGURE 24. USING A PNP TRANSISTOR TO TRANSFORM 3.3V INTO 1.8V....................................................................................132 FIGURE 25. RECEPTION DATA TIMING OF MII/SNI/SMI INTERFACE...........................................................................................136 FIGURE 26. TRANSMISSION DATA TIMING OF MII/SNI/SMI INTERFACE.....................................................................................136 FIGURE 27. UTP APPLICATION FOR TRANSFORMER WITH CONNECTED CENTRAL TAP................................................................141 FIGURE 28. UTP APPLICATION FOR TRANSFORMER WITH SEPARATE CENTRAL TAP....................................................................142 FIGURE 29. 100BASE-FX WITH 3.3V FIBER TRANSCEIVER APPLICATION...................................................................................143 FIGURE 30. 100BASE-FX WITH 5V FIBER TRANSCEIVER APPLICATION......................................................................................144

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RTL8305SC Datasheet 1. General Description

The RTL8305SC is a 5-port Fast Ethernet switch controller that integrates memory, five MACs, and five physical layer transceivers for 10Base-T and 100Base-TX operation into a single chip. All ports support 100Base-FX, which shares pins (TX+-/RX+-) with UTP ports and needs no SD+/- pins, a development using Realtek proprietary technology. To compensate for the lack of auto-negotiation in 100Base-FX applications, the RTL8305SC can be forced into 100Base-FX half or full duplex mode, and can enable or disable flow control in fiber mode.

The five ports are separated into three groups (GroupX/GroupY/Port4) for flexible port configuration using strapping pins upon reset. The SetGroup pin is used to select port members in GroupX and GroupY. When the port members have been determined, you may use a mode selection pin (GxMode/Gymode/P4Mode[1:0]) to select operating interfaces such as 10/100Base-TX, 100Base-FX. Each group has four pins for selecting initial port status upon reset (ANEG/Force, 100/10, Full/Half, Enable/Disable Flow Control). Upon reset, in addition to using strapping pins, a CPU can also configure the RTL8305SC via the MDC/MDIO interface.

The fifth port (port 4) supports an external MAC and an external PHY interface. The external MAC interface can be set to PHY mode MII, PHY mode SNI, or MAC mode MII to work with a routing engine, HomePNA, or VDSL transceiver. The external PHY interface can be set to PHY mode MII in the digital interface, and UTP or fiber in the differential interface. In order to accomplish diagnostics in complex network systems, the RTL8305SC also provides a loopback feature in each port for a variable CPU system.

The RTL8305SC contains a 1K-entry address lookup table and supports a 16-entry CAM to avoid hash collisions and to maintain forwarding performance. The 1K-entry table provides read/write access from the SMI interface, and each of the entries can be configured as a static entry. A static entry indicates that this entry is controlled by the external management processor and automatic aging and learning of the entry will not take place. The RTL8305SC supports IEEE 802.3x full-duplex flow control and back-pressure half-duplex flow control. A broadcast storm filtering function is provided to filter unusual broadcast storm issues, and an intelligent switch engine prevents Head-Of -Line blocking problems.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 1 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet The RTL8305SC supports 16 VLAN groups. These can be configured as port-based VLANs and/or IEEE 802.1Q tag-based VLANs. Two ingress filtering and egress filtering options provide flexible VLAN configuration:

• Ingress filtering option 1: The Acceptable Frame Type of the Ingress Process can be set to ‘Admit All’ or ‘Admit All Tagged’. • Ingress filtering option 2: ‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set. • Egress filtering option 1: ‘Forward’ or ‘Discard’ ARP broadcast frames. • Egress filtering option 2: ‘Forward’ or ‘Discard’ Leaky VLAN frames.

The RTL8305SC supports several types of QoS functions with two-level priority queues to improve multimedia or real-time networking applications. The QoS functions are based on:

• Port-based priority

• 802.1Q VLAN priority tag

• The TOS/DS (DiffServ) field of TCP/IP

When the QoS function is enabled, a VLAN tag can be inserted or removed at the output port. The RTL8305SC will insert a Port VID (PVID) for untagged frames or remove the tag from tagged frames. The RTL8305SC also supports a special insert VLAN tag function to separate traffic from WAN and LAN sides in Router and Gateway applications.

In router applications, the router may want to know which input port this packet came from. The RTL8305SC supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress. Using this function, VID information carried in the VLAN tag will be changed to PVID. The RTL8305SC also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.

Maximum packet length can be 1536 or 1552 bytes according to the initial configuration (strapping upon reset). The filtering function is supported for the 802.1D specified reserved multicast addresses (01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F).

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RTL8305SC Datasheet The RTL8305SC provides flexible LED functions for diagnostics. These include: Three combinations of link, activity, speed, duplex and collision, that are ideal for bi-color LED displays. The RTL8305SC also provides a loop detection function and alarm, for network existence notification, with an output pin that can be designed as a visual LED or a status input pin for a CPU.

A power saving mode is implemented on a per-port basis. Each port automatically enters power saving mode 10 seconds after the cable is disconnected from it. The RTL8305SC also implements a power down mode on a per-port basis. Users can set MII Reg.0.11 to force the corresponding port to enter power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO management interface). Each physical layer channel of the RTL8305SC consists of a 4B5B encoder/decoder, a Manchester encoder/decoder, a scrambler/de-scrambler, a transmit output driver, output wave shaping filters, a digital adaptive equalizer, a PLL circuit, and a DC restoration circuit for clock/data recovery. Friendly crossover auto detection and correction functions are also supported for easy cable connection.

The integrated chip benefits from low power consumption, advanced functions with flexible configuration for 5-port SOHO switch, Home Gateway, xDSL/Cable router, and other IA applications.

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RTL8305SC Datasheet 2. Features

󰂄 5-port integrated switch controller with

memory and transceiver for 10Base-T and 100Base-TX with:

󰂋 5-port 10/100M UTP or 󰂋 4-port 10/100M UTP + 1-port

󰂄 Supports broadcast storm filtering

function 󰂄 Flow control fully supported:

󰂋 Half duplex: back pressure flow

MII/SNI or

󰂋 4-port 10/100M UTP + 1-port MAC

MII/SNI + 1-port PHY MII 󰂄 Supports the fifth port MAC circuit as

PHY mode MII, SNI for router

applications, and MAC mode MII for HomePNA or VDSL solutions 󰂄 Supports the fifth port PHY circuit as

PHY mode MII for router and Gateway applications 󰂄 All ports support 100Base-FX with

optional flow control enable/disable and full/half-duplex setting 󰂄 Supports FEFI function for fiber

application 󰂄 Non-blocking wire-speed reception and

transmission and non-head-of-line-blocking forwarding 󰂄 Fully compliant with

IEEE 802.3/802.3u auto-negotiation function 󰂄 Built-in high-efficiency SRAM for

packet buffer, with 1K-entry lookup table and 16-entry CAM

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

control

󰂋 Full duplex: IEEE 802.3x flow

control 󰂄 Supports SMI (Serial Management

Interface: MDC/MDIO) for programming and diagnostics 󰂄 Supports loop detection function with

one LED to indicate the existence of a loop 󰂄 Supports MAC and PHY loopback

function for diagnosis 󰂄 Supports up to 16 VLAN groups 󰂄 Flexible 802.1Q port/tag-based VLAN 󰂄 ARP VLAN for broadcast packets 󰂄 Leaky VLAN for unicast packets 󰂄 VLAN tag Insert/Remove function 󰂄 Supports QoS function on each port:

󰂋 QoS based on: (1) Port-based,

(2) VLAN tag, (3) TCP/IP header’s

TOS/DS

󰂋 Supports two-level priority queues 󰂋 Weighted round robin service

4 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 󰂄 Supports special VLAN tag insert or

remove function on per-port basis (egress) to separate WAN traffic from LAN traffic 󰂄 Optional 1536 or 1552 byte maximum

packet length 󰂄 Supports reserved control frames

(DID=0180C2000003~0180C200000F) filtering function 󰂄 Flexible LED indicators for link,

activity, speed, full/half duplex, and collision 󰂄 LEDs blink upon reset for LED

diagnostics 󰂄 Supports two power reduction methods:

󰂋 Power saving mode by cable

󰂄 Robust baseline wander correction for

improved 100Base-TX performance 󰂄 Optional MDI/MDIX auto crossover

for plug-and-play 󰂄 Physical layer port Polarity Detection

and Correction function 󰂄 Optional EEPROM interface for

configuration 󰂄 25MHz crystal or 3.3V OSC input 󰂄 Single 3.3V power input can be

transformed to 1.8V via a low-cost external BJT transistor 󰂄 Low power, 1.8/3.3V, 0.18µm CMOS

technology, 128-pin PQFP package

detection

󰂋 Power down mode (via PHY

register 0.11)

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RTL8305SC Datasheet 3. Block Diagram

IBREFWaveformShapingRX+-[0]TX+-[0]10Base-T or100Base-TPHYceiverMAC0SwitchEngine0LookupTableRX+-[1]TX+-[1]10Base-T or100Base-TPHYceiverMAC1SwitchEngine1PacketBufferRX+-[2]TX+-[2]10Base-T or100Base-TPHYceiverMAC2SwitchEngine2RX+-[3]TX+-[3]10Base-T or100Base-TPHYceiverMAC3SwitchEngine3DISBRDCTRLENBKPRSRESET#RX+-[4]TX+-[4]10Base-T or100Base-TPHYceiverMAC4SwitchEngine4GlobalFunctionX1X2CK25MOUTPHY2PRXCPHY2PRXDVPHY2PRXD[3:0]PHY2PTXCPHY2PTXENPHY2PTXD[3:0]PHY2PCOLMTXC/PRXCMTXEN/PRXDVMTXD[3:0]/PRXD[3:0]MRXC/PTXCMRXDV/PTXENMRXD[3:0]/PTXD[3:0]MCOL/PCOLP4LNKSTA#P4DUPSTA/P4FULLP4SPDSTA/P4SPD100P4FLCTRL/P4ENFCP4MODE[1:0]DISDUALMIISEL_MIIMACPHYModeMII5-port 10/100Mbps Single-Chip Dual MII Switch Controller

PHY InterfacerEN_RST_BLNKMACModeMIIPHYModeMII/SNIModeSelectCircuitLED_BLNK_TIMELEDControlLED_SPD[4:0]LED_ACT[4:0]LED_DUP[4:0]LED_ADD[4:0]MAC Interface Figure 1. Block Diagram

6

Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 4. Pin Assignments

DGNDLED_ADD[2]/DISLEAKYDVDD18LED_DUP[3]/GYMODELED_SPD[3]/DISARPLED_ACT[3]/EN48PASS1LED_ADD[3]/GXMODELED_DUP[4]/SETGROUPDGNDLED_SPD[4]/DISVLANLED_ACT[4]LED_ADD[4]/DISTAGPRILOOPLED#/ENDEFERPHY2PCOL/LED_BLNK_TIMEDISPORTPRI[4](PHY2PTXD[3])DVDD33DISPORTPRI[3](PHY2PTXD[2])DISPORTPRI[2](PHY2PTXD[1])DISPORTPRI[1](PHY2PTXD[0])DISPORTPRI[0](PHY2PTXEN)PHY2PTXC/QWEIGHT[1]PHY2PRXC/QWEIGHT[0]PHY2PRXDV/DISBRDCTRLDGNDPHY2PRXD[3]/ENBKPRSPHY2PRXD[2]/GYENFCPHY2PRXD[1]/GXENFCSDA_MDIOSCL_MDCPHY2PRXD[0]/ENEEPROMITEST6EN_RST_BLNKDVDD18EN_AUTOXOVERSEL_MIIMAC#/DISDSPRIMRXD[3]/PTXD[3]MRXD[2]/PTXD[2]ITEST5P4ANEG/LED_ACT[2]GXANEG/LED_SPD[2]GYANEG/LED_DUP[2]

DVDD33

GXSPD100/LED_ADD[1]GYSPD100/LED_ACT[1]GXFULL/LED_SPD[1]GYFULL/LED_DUP[1]ENFORWARD/LED_ADD[0]

DGND

BCINDROP/LED_ACT[0]MAX1536/LED_SPD[0]

LED_DUP[0]CK25MOUT

OSCIHVDD33AVDD18

X1X2AGNDVCTRLDTEST2DTEST1AGNDIBREFAVDD18

10310410510610710810911011111211311411511611711811912012112212312412512612712810210110099989796959493929190898887868584838281807978777675747372717069686766656463626160595857565554535251504948474645444342414039RTL8305SCDGND

MRXD[1]/PTXD[1]DVDD33

MRXD[0]/PTXD[0]MRXDV/PTXENMRXC/PTXCMCOL/PCOL

MTXD[3]/PRXD[3]/P4IRTAG[1]MTXD[2]/PRXD[2]/P4IRTAG[0]MTXD[1]/PRXD[1]/LEDMODE[1]MTXD[0]/PRXD[0]/LEDMODE[0]DVDD18

MTXEN/PRXDVMTXC/PRXCDGND

P4LNKSTA#

P4DUPSTA/P4FULLP4SPDSTA/P4SPD100P4FLCTRL/P4ENFCP4MODE[0]P4MODE[1]DVDD18DISDUALMIIITEST4RESET#DGND

AVDD18RXIN[0]RXIP[0]AGNDTXOP[0]TXON[0]AVDD18AVDD18TXON[1]TXOP[1]AGNDRXIP[1]RXIN[1]AVDD18AVDD18RXIN[2]RXIP[2]AGNDTXOP[2]TXON[2]AVDD18AVDD18TXON[3]TXOP[3]AGNDRXIP[3]RXIN[3]AVDD18AVDD18RXIN[4]RXIP[4]AGNDTXOP[4]TXON[4]AVDD18ITEST1ITEST2ITEST31234567891011121314151617181920212223242526272829303132333435363738

Figure 2. Pin Assignments

Note: When DISDUALMII=1, the function of pins 83~86 and pin 88 follows the names before the parenthesis ‘( )’.

When DISDUALMII=0, pin names in parenthesis ‘( )’ will become functional and original pin functions will not apply.

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RTL8305SC Datasheet ‘Type’ codes used in the following tables: A=Analog; D=Digital, I=Input; O=Output, PU=Internal pull-up, PD=Internal pull-down.

Table 1. Pin Assignments

Name

AVDD18 RXIN[0] RXIP[0] AGND TXOP[0] TXON[0] AVDD18 AVDD18 TXON[1] TXOP[1] AGND RXIP[1] RXIN[1] AVDD18 AVDD18 RXIN[2] RXIP[2] AGND TXOP[2] TXON[2] AVDD18 AVDD18 TXON[3] TXOP[3] AGND RXIP[3] RXIN[3] AVDD18 AVDD18 RXIN[4] RXIP[4] AGND TXOP[4] TXON[4] AVDD18 ITEST1 ITEST2 ITEST3 DGND RESET# ITEST4

DISDUALMII DVDD18 P4MODE[1] P4MODE[0]

P4FLCTRL/P4ENFC P4SPDSTA/P4SPD100 P4DUPSTA/P4FULL P4LNKSTA# DGND

MTXC/PRXC

MTXEN/PRXDV/Internal DVDD18

MTXD[0]/PRXD[0]/LEDMODE[0] MTXD[1]/PRXD[1]/LEDMODE[1] MTXD[2]/PRXD[2]/P4IRTAG[0] MTXD[3]/PRXD[3]/P4IRTAG[1] MCOL/PCOL MRXC/PTXC MRXDV/PTXEN MRXD[0]/PTXD[0] DVDD33

MRXD[1]/PTXD[1] DGND

Pin No.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Type

AVDD AI AI AGND AO AO AVDD AVDD AO AO AGND AI AI AVDD AVDD AI AI AGND AO AO AVDD AVDD AO AO AGND AI AI AVDD AVDD AI AI AGND AO AO AVDD DGND I IPU DVDD IPU IPU IPU IPU IPU IPU DGND I/OPU I/OPU DVDD I/OPU I/OPU I/OPU I/OPU I/OPD I/OPU IPD IPU DVDD IPU DGND

Name

ITEST5 MRXD[2]/PTXD[2] MRXD[3]/PTXD[3]

SEL_MIIMAC#/DISDSPRI EN_AUTOXOVER DVDD18

EN_RST_BLNK ITEST6

PHY2PRXD[0]/ENEEPROM SCL_MDC SDA_MDIO

PHY2PRXD[1]/GXENFC PHY2PRXD[2]/GYENFC PHY2PRXD[3]/ENBKPRS DGND

PHY2PRXDV/DISBRDCTRL PHY2PRXC/QWEIGHT[0] PHY2PTXC/QWEIGHT[1]

DISPORTPRI[0] (PHY2PTXEN) DISPORTPRI[1] (PHY2PTXD[0]) DISPORTPRI[2] (PHY2PTXD[1]) DISPORTPRI[3] (PHY2PTXD[2]) DVDD33

DISPORTPRI[4] (PHY2PTXD[3]) PHY2PCOL/LED_BLNK_TIME LOOPLED#/ENDEFER LED_ADD[4]/DISTAGPRI LED_ACT[4]

LED_SPD[4]/DISVLAN DGND

LED_DUP[4]/SETGROUP LED_ADD[3]/GXMODE LED_ACT[3]/EN48PASS1 LED_SPD[3]/DISARP LED_DUP[3]/GYMODE DVDD18

LED_ADD[2]/DISLEAKY DGND

LED_ACT[2]/P4ANEG LED_SPD[2]/GXANEG LED_DUP[2]/GYANEG DVDD33

LED_ADD[1]/GXSPD100 LED_ACT[1]/GYSPD100 LED_SPD[1]/GXFULL LED_DUP[1]/GYFULL

LED_ADD[0]/ENFORWARD DGND

LED_ACT[0]/BCINDROP LED_SPD[0]/MAX1536 LED_DUP[0] CK25MOUT OSCI HVDD33 AVDD18 X1 X2 AGND VCTRL DTEST2 DTEST1 AGND IBREF AVDD18

Pin No.

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

Type

IPU IPU I/OPU IPU DVDD IPU IPU I/OPU I/OPU IPU IPU IPU DGND IPU IPU IPU IPU IPU IPU IPU DVDD IPU IPU I/OPU I/OPU I/OPU I/OPU DGND I/OPU I/OPU I/OPU I/OPU I/OPU DVDD I/OPU DGND I/OPU I/OPU I/OPU DVDD I/OPU I/OPU I/OPU I/OPU I/OPU DGND I/OPU I/OPU I/OPU O I AVDD AVDD I O AGND O AGND A AVDD

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 8 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 5. Pin Descriptions

‘Type’ codes used in the following tables: A=Analog; D=Digital, I=Input; O=Output, PU=Internal pull-up, PD=Internal pull-down.

Upon Reset: Defined as a short time after the end of a hardware reset. After Reset: Defined as the time after the specified ‘Upon Reset’ time.

5.1. Media Connection Pins Table 2. Media Connection Pins

Pin Name RXIP[4:0] RXIN[4:0] TXOP[4:0] TXON[4:0]

Pin No. Type

I 2, 3, 12, 13,

16, 17, 26, 27, 30, 31 5, 6, 9, 10, 19, 20, 23, 24, 33, 34

O

Drive (mA) Description

Differential Receive Data Input

Shared by 100Base-TX, 10Base-T, and 100Base-FX.

UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].

Differential Transmit Data Output

Shared by 100Base-TX, 10Base-T, and 100Base-FX.

UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].

5.2. Port 4 Configuration Pins Table 3. Port 4 Configuration Pin Definitions

Pin Name

Pin No.

Type

Drive (mA) Description

Port 4 Configuration Pin Definitions

Disable Dual MII Interface Function

This pin disables or enables the Dual MII interface function of port 4. 1: Disable 0: Enable

When enabled, the MAC circuit of port 4 can be set as MAC mode MII, PHY mode MII, or PHY mode SNI. The PHY circuit of port 4 is set as PHY mode MII.

The PHY circuit of port 4 can optionally be set as UTP or fiber mode according to the P4MOD[1:0] configuration.

DISDUALMII 42 IPU

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 9 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Pin Name

Pin No.

Type

Drive (mA) Description

Port 4 Configuration Pin Definitions

When DISDUALMII1:

Select Port 4 MAC Circuit Operating Mode:

11: UTP/MAC mode MII 10: 100Base-FX mode 01: PHY mode MII 00: PHY mode SNI

When DISDUALMII=0,

I. Select Port 4 MAC Circuit Operating Mode: 1x: MAC mode MII

01: PHY mode MII 00: PHY mode SNI 11: Port 4 PHY Circuit Operating Mode:

Note: Provides PHY mode MII only when DISDUALMII=0.

Port 4 Link Status for MAC

This pin determines the link status of the Port 4 MAC in real-time when the Port 4 MAC is in MAC mode MII/PHY mode MII/PHY mode SNI regardless of whether the Port 4 PHY circuit interface is disabled or enabled in PHY mode MII. This pin is low active. Pulling this pin down sets the link status of the PHY 5 MII register to 1.2. 1: No Link 0: Link

P4MODE[1:0]=11 and DISDUALMII=1 (UTP/MAC mode MII)

This pin determines the link status of MAC mode MII only in real time. The link status of UTP mode is provided by the internal PHY in real time. If both the UTP and MII ports are linked OK, UTP has higher priority.

P4MODE[1:0]=11 and DISDUALMII=0 (MAC mode MII) This pin determines the link status of MAC mode MII only in

=real time.

P4MODE[1:0]=10 (100Base-FX mode)

This pin does nothing. The internal PHY will provide the link status to the MAC in real time.

P4MODE[1:0]=01 (PHY mode MII)

This pin determines the link status of Port 4 in real time.

P4MODE[1:0]=00 (PHY mode SNI)

This pin determines the link status of Port 4 in real time.

When DISDUALMII=1, this pin should be left floating in UTP or FX mode, and pulled down in MAC mode MII/PHY mode MII/PHY mode SNI.

Regardless of whether DISDUALMII=1 or=0, this pin provides the link status to the Port 4 MAC part in PHY 5 MII register 1.2 when the Port 4 MAC part is configured in MAC mode MII/PHY mode MII/PHY mode SNI.

10

Track ID: JATR-1076-21 Rev. 1.2

P4MODE[1:0] 44, 45 IPU

P4LNKSTA# 49 IPU

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet Pin Name

Pin No.

Type

Drive (mA) Description

Port 4 Configuration Pin Definitions

Port 4 Duplex Status

Port 4 initial configuration pin for duplex upon reset for PHY in UTP or FX mode, and strap duplex status for MAC of other modes upon reset. 1: Full duplex 0: Half duplex

P4MODE[1:0]=11 (UTP/MAC mode MII)

This pin provides the initial duplex configuration of the PHY part upon reset when Port 4 operates in UTP mode. If Port 4 operates in MAC mode MII, this pin straps the initial duplex status for the MAC part upon reset.

P4MODE[1:0]=10 (100Base-FX mode)

This pin provides the initial duplex register configuration of the PHY part upon reset (FX). The duplex status of the MAC part is provided by the internal PHY in real time after reset.

P4MODE[1:0]=01 (PHY mode MII)

This pin straps the initial duplex status of Port 4 upon reset.

P4MODE[1:0]=00 (PHY mode SNI)

This pin straps the initial duplex status of Port 4 upon reset.

In MAC mode MII/PHY mode MII/PHY mode SNI, the configuration of this pin will set the duplex status of the internal register upon reset.

P4DUPSTA 48 IPU

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RTL8305SC Datasheet Pin Name

Drive (mA) Description

Port 4 Configuration Pin Definitions

P4SPDSTA 47 IPU Port 4 Speed Status

Port 4 initial configuration pin for speed status upon reset for PHY of UTP mode only, and strap speed status for MAC of other modes upon reset. 1: 100Mbps 0: 10Mbps

P4MODE[1:0]=11 (UTP/MAC mode MII)

This pin provides the initial speed configuration of the PHY part upon reset when Port 4 operates in UTP mode. If Port 4 operates in MAC mode MII, this pin straps the initial speed status for the MAC part upon reset.

P4MODE[1:0]=10 (100Base-FX mode)

The speed is dedicated to 100M and this pin should be left floating as it is irrelevant.

P4MODE[1:0]=01 (PHY mode MII)

This pin straps the initial speed status of Port 4 upon reset.

P4MODE[1:0]=00 (PHY mode SNI)

The speed is dedicated to 10MHz. This pin should be pulled down.

In order to provide 100M as the default value for PHY, this pin is set as high active.

Pin No.

Type

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RTL8305SC Datasheet Pin Name P4FLCTRL/ P4EnFC

Pin No.

Type

Drive (mA) Description

Port 4 Configuration Pin Definitions Port 4 Flow Control

Port 4 initial configuration pin for flow control upon reset for PHY of UTP and FX mode, and strap flow control status for MAC of other modes upon reset. 1: Enable Flow Control ability 0: Disable Flow Control ability

P4MODE[1:0]=11 (UTP/MAC mode MII)

This pin provides the initial flow control configuration of the PHY part upon reset when Port 4 operates in UTP mode. If Port 4 operates in MAC mode MII, this pin straps the initial flow control status for the MAC part upon reset.

P4MODE[1:0]=10 (100Base-FX mode)

This pin provides the initial configuration of flow control for the PHY part upon reset (FX).

P4MODE[1:0]=01 (PHY mode MII)

This pin straps the initial flow control status of Port 4 upon reset.

P4MODE[1:0]=00 (PHY mode SNI)

Flow control should be disabled. This pin must be pulled down.

In order to enable flow control ability for the PHY, this pin is set as high active.

46 IPU

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RTL8305SC Datasheet Pin Name SEL_MIIMAC#/DisDSPri /(P4PHY_ MODE)

Pin No.

Type

Drive (mA) Description

Port 4 Configuration Pin Definitions

4 Output After Reset = SEL_MIIMAC# used for LED

When P4MODE[1:0]=11 and DISDUALMII=1, this pin indicates whether the UTP path or the MII MAC path is selected. Otherwise, this pin has no use.

The LED statuses are represented as active-low or high depending on input strapping

If Input=1: Output 0=MII MAC port is selected. 1=UTP is selected.

If Input=0: Output 1=MII MAC port is selected. 0=UTP is selected.

When P4MODE[1:0]=11 and DISDUALMII=1, the

RTL8305SC supports UTP/MII MAC auto-detection function via the link status of Port 4 UTP and the P4LNKSTA# pin setting. UTP has higher priority than MAC mode MII.

Input Upon Reset when DISDUALMII=1, DisDSPri. Disable Differentiated Service Priority. 1: Disable DS priority 0: Enable DS priority

Input Upon Reset when DISDUALMII=0, P4PHY_MODE. Select the operating mode of Port 4 differential pair. 1: UTP mode 0: FX mode

68 I/OPU

5.3. Port 4 MAC Circuit Interface Pins The external device must be 3.3V compatible since the digital output of the RTL8305SC is 3.3V.

Table 4. Port 4 MAC Circuit Interface Pin Definitions

Pin Name MRXD[3:0]/ PTXD[3:0]

Pin No.61, 63, 66, 67

Type Drive (mA)Description IPU For MAC mode MII, these pins are MRXD[3:0], MII receive

data nibble.

For PHY mode MII, these pins are PTXD[3:0], MII transmit data nibble.

For PHY mode SNI, PTXD[0] is serial transmit data.

60 IPD For MAC mode MII, this pin represents MRXDV, MII receive

data valid.

For PHY mode MII, this pin represents PTXEN, MII transmit enable.

For PHY mode SNI, this pin represents PTXEN, transmit enable.

59 I/OPU 8 For MAC mode MII, this is a receive clock (MRXC acts as

input).

For PHY mode MII/PHY mode SNI, it is a transmit clock (PTXC acts as output).

14

Track ID: JATR-1076-21 Rev. 1.2

MRXDV/PTXEN

MRXC/PTXC

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet Pin Name MCOL/PCOL

Pin No.Type Drive (mA)Description 58 I/OPD 4 For MAC mode MII, this pin represents MCOL collision (acts as

input).

For PHY mode MII/PHY mode SNI, this pin represents PCOL collision (acts as output).

MTXD[3]/PRXD[3] 57 I/OPU 4 Output After Reset. /P4IRTag[1] For MAC mode MII (P4MODE[1:0]=11), these pins are

MTXD[3:0], MII transmit data of MAC.

For PHY mode MII (P4MODE[1:0]=01), these pins are MTXD[2]/PRXD[2] 56

PRXD[3:0], MII receive data of PHY. /P4IRTag[0]

For PHY mode SNI (P4MODE[1:0]=00), PRXD[0] is SNI serial

receive data.

Input Upon Reset: P4IRTag[1:0] Insert/Remove VLAN tags of Port 4.

11=Do not insert/remove VLAN tags to/from packets. 10=Insert VLAN tags to non-tagged packets. 01=Remove tag from tagged packet.

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets.

These pins are used for Port 4 only. Use serial EEPROM for other ports.

MTXD[1]/PRXD[1] 55 I/OPU 4 Output After Reset. /LEDMODE[1] For MAC mode MII (P4MODE[1:0]=11), these pins are

MTXD[3:0], MII transmit data of MAC.

For PHY mode MII (P4MODE[1:0]=01), these pins are MTXD[0]/PRXD[0] 54

PRXD[3:0], MII receive data of PHY. /LEDMODE[0]

For PHY mode SNI (P4MODE[1:0]=00), PRXD[0] is SNI serial

receive data.

Input Upon Reset: LEDMODE[1:0]

Each port has four LED indicator pins. Each pin has different indicator meanings set by pins, LEDMODE[1:0].

LEDMODE[1:0]=11: Speed + Link/Act + Duplex/Col + Link/Act/Spd.

LEDMODE[1:0]=10: Speed + Act + Duplex/Col+Bi-color Link/Active.

LEDMODE[1:0]=01: Speed + RxAct + TxAct + Link. LEDMODE[1:0]=00: Reserved.

All LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color LED mode, whose polarity depends on Spd status.

Link/Act/Spd: Link, Activity, and Speed Indicator. ON for link established. Blinking every 43ms when the corresponding port is transmitting or receiving at 100Mbps. Blinking every 120ms when the port is transmitting or receiving at 10Mbps.

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RTL8305SC Datasheet Pin Name

MTXEN/PRXDV /Internal

Pin No.Type Drive (mA)Description 52 I/OPD 4 Output After Reset.

For MAC mode MII, this pin represents MTXEN, MII transmit enable.

For PHY mode MII, this pin represents PRXDV, MII received data valid.

For PHY mode SNI, this pin represents PRXDV, received data valid.

Input Upon Reset. Internal Use

51 I/OPU 8 For MAC mode MII, it is a transmit clock (MTXC acts as input).

For PHY mode MII/PHY mode SNI, it is a receive clock (PRXC acts as output).

MTXC/PRXC

5.4. Port 4 PHY Circuit Interface Pins The external device must be 3.3V compatible as the digital output of the RTL8305SC is 3.3V.

Table 5. Port 4 PHY Circuit Interface Pin Definitions

Pin Name

DISPORTPRI[4] (PHY2PTXD[3])

Pin No. Type Drive (mA)Description 88 IPU - DISDUALMII=1, Enable Port based priority QoS function of

port 4.

DisPortPri[4]: 1=Disable port 4 priority. 0=Enable port 4 priority.

DISDUALMII=0, PHY mode MII Transmit Data Nibble.

For PHY mode MII, this pin is PHY2PTXD[3]. DISPORTPRI[4] power on strapping is not supported when DISDUALMII=0. This configuration can be set from the MII register.

86 IPU - DISDUALMII=1, Enable Port based priority QoS function of

port 3.

DisPortPri[3]: 1=Disable port 3 priority. 0=Enable port 3 priority.

DISDUALMII=0, PHY mode MII Transmit Data Nibble.

For PHY mode MII, this pin is PHY2PTXD[2]. DISPORTPRI[3] power on strapping is not supported when DISDUALMII=0. This configuration can be set from the MII register.

85 IPU - DISDUALMII=1, Enable Port based priority QoS function of

port 2.

DisPortPri[2]: 1=Disable port 2 priority. 0=Enable port 2 priority.

DISDUALMII=0, PHY mode MII Transmit Data Nibble.

For PHY mode MII, this pin is PHY2PTXD[1]. DISPORTPRI[2] power on strapping is not supported when DISDUALMII=0. This configuration can be set from the MII register.

DISPORTPRI[3] (PHY2PTXD[2])

DISPORTPRI[2] (PHY2PTXD[1])

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RTL8305SC Datasheet Pin Name

DISPORTPRI[1] (PHY2PTXD[0])

Pin No. Type Drive (mA)Description 84 IPU - DISDUALMII=1, Enable Port based priority QoS function of

port 1.

DisPortPri[1]: 1=Disable port 1 priority. 0=Enable port 1 priority.

DISDUALMII=0, PHY mode MII Transmit Data Nibble.

For PHY mode MII, this pin is PHY2PTXD[0]. DISPORTPRI[1] power on strapping is not supported when DISDUALMII=0. This configuration can be set from the MII register.

83 IPU - DISDUALMII=1, Enable Port based priority QoS function of

port 0.

DisPortPri[0]: 1=Disable port 0 priority. 0: Enable port 0 priority.

DISDUALMII=0, PHY mode MII Transmit Data Enable.

For PHY mode MII, this pin is PHY2PTXEN. DISPORTPRI[0] power on strapping is not supported when DISDUALMII=0. This configuration can be set from the MII register.

For Dual MII application, this pin should be pulled low (about 1k ohm) in the external circuit.

89 I/OPU 4 Output After Reset: DISDUALMII=0, PHY mode MII PCOL.

For PHY mode MII, this pin represents PCOL collision (acts as output).

Input Upon Reset: LED Blink Time.

This pin selects the blinking speed of the activity and collision LEDs.

1: On 43ms, then Off 43ms 0: On 120ms, then Off 120ms

Power on strapping is independent of DISDUALMII configuration.

82 I/OPU 8 Output After Reset: DISDUALMII=0, PHY mode MII Transmit/

Receive Data Clock.

For PHY mode MII, this is transmit/receive data clock,

PTXC/PRXC (acts as output). 81

Input Upon Reset: Weighted round robin ratio of priority queue. The frame service rate of High-priority queue: Low-priority queue QWEIGHT[1:0]=11: 16:1

QWEIGHT[1:0]=10: Always high priority queue first QWEIGHT[1:0]=01: 8:1 QWEIGHT[1:0]=00: 4:1

Power on strapping is independent of DISDUALMII configuration.

DISPORTPRI[0] (PHY2PTXEN)

PHY2PCOL /LED_BLNK_ TIME

PHY2PTXC /QWEIGHT[1]

PHY2PRXC /QWEIGHT[0]

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RTL8305SC Datasheet Pin Name

PHY2PRXD[3] /ENBKPRS

Pin No. Type Drive (mA)Description 78 I/OPU 4 Output After Reset: DISDUALMII=0, PHY mode MII Receive

Data Nibble (acts as output).

For PHY mode MII, this pin is PHY2PRXD[3].

Input Upon Reset: Enable Back Pressure.

This pin sets back pressure in half duplex mode on all UTP ports. 1: Enable 0: Disable

Power on strapping is independent of DISDUALMII configuration.

77 I/OPU 4 Output After Reset: DISDUALMII=0, PHY mode MII Receive

Data Nibble (acts as output).

For PHY mode MII, this pin is PHY2PRXD[2].

Input Upon Reset: GroupY Enable Flow Control ability.

1: Enable Reg4.10 (NWAY Full duplex only), or ‘Enable Force Full pause ability of Force mode (UTP Force mode or FX mode)’, or ‘Enable Force Half Back Pressure ability of Force mode (UTP Force mode or FX mode)’

0: Disable Reg4.10 (NWAY Full duplex only), or ‘Disable Force Full pause ability of Force mode (UTP Force mode or FX mode)’, or ‘Disable Force Half Back Pressure ability of Force mode (UTP Force mode or FX mode)’

Strap after reset for initial value of Group Y ‘UTP NWAY Full’, or ‘UTP Force Full or Half mode’, or ‘FX Full or Half mode’. Power on strapping is independent of DISDUALMII configuration.

76 I/OPU 4 Output After Reset: DISDUALMII=0, PHY mode MII Receive

Data Nibble (acts as output).

For PHY mode MII, this pin is PHY2PRXD[1].

Input Upon Reset: GroupX Enable Flow Control ability:

1: Enable Reg4.10 (NWAY Full duplex only), or ‘Enable Force Full pause ability of Force mode (UTP Force mode or FX mode)’, or ‘Enable Force Half Back Pressure ability of Force mode (UTP Force mode or FX mode)’

0: Disable Reg4.10 (NWAY Full duplex only), or ‘Disable Force Full pause ability of Force mode (UTP Force mode or FX mode)’, or ‘Disable Force Half Back Pressure ability of Force mode (UTP Force mode or FX mode)’

Strap after reset for initial value of Group X ‘UTP NWAY Full’, or ‘UTP Force Full or Half mode’, or ‘FX Full or Half mode’. Power on strapping is independent of DISDUALMII configuration.

PHY2PRXD[2] /GYENFC

PHY2PRXD[1] /GXENFC

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RTL8305SC Datasheet Pin Name

PHY2PRXD[0] /ENEEPROM

Pin No. Type Drive (mA)Description 73 I/OPU 4 DISDUALMII=0, PHY mode MII Receive Data Nibble (acts as

output).

For PHY mode MII, this pin is PHY2PRXD[0].

Enable EEPROM: This pin sets the RTL8305SC to enable loading of the serial EEPROM upon reset. 1: Enable 0: Disable

These pins have internal 75k ohm pull-high resistors. Power on strapping is independent of DISDUALMII configuration.

80 I/OPU 4 DISDUALMII0, PHY mode MII Receive Data Valid.

For PHY mode MII, this pin represents PRXDV.

Disable Broadcast Storm Control. 1: Disable 0: Enable

The RTL8305SC will disable this function when pin DISBRDCTRL is left floating.

This pin has an internal 75k ohm pull-high resistor. Power on strapping is independent of DISDUALMII configuration.

PHY2PRXDV /DISBRDCTRL

5.5. Miscellaneous Pins Pin Name X1

Pin No. Type 120 I

=

Table 6. Miscellaneous Pins

Drive (mA)Description

A 25MHz crystal input

The clock tolerance is +-50ppm. When using an oscillator, this pin should be tied to ground.

For crystal input

When using an oscillator, this pin should be left floating.

A 25MHz clock from oscillator is fed to this pin

The X1 should be tied to ground and X2 should be left floating in this application.

If a 25MHz clock is from crystal via X1 and X2, this pin should be left floating.

8 A 25MHz clock output

This pin is used to support an extra 25M clock for an external device (for example: HomePNA PHY). If this clock output is not used, this pin should be left floating.

Active low reset signal

To complete the reset function, this pin must be asserted for at least 1ms. After reset, about 30ms is needed for the RTL8305SC to complete internal test functions and initialization. This pin is a Schmitt input.

19

Track ID: JATR-1076-21 Rev. 1.2

X2 OSCI

121 117

O I

CK25MOUT 116 O

RESET# 40 I

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RTL8305SC Datasheet Pin Name IBREF VCTRL

Pin No. Type 127 A 123

O

Drive (mA)Description

Control transmit output waveform Vpp

This pin should be grounded through a 1.96KΩ resistor.

4 Voltage control to external regulator

This signal controls a power PNP transistor to generate the 1.8V power supply.

Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating Reserved pin for internal use. Should be left floating

ITEST1

ITEST2 ITEST3 ITEST4 ITEST5 ITEST6 DTEST2 DTEST1 36 37 38 41 65 72 124 125

5.6. Port LED Pins Each port has four LED indicator pins. Each pin may have different indicator meanings as set by pins LEDMODE[1:0].

All LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color LED mode, whose polarity depends on Spd status.

Those pins that are dual function pins are output for LED or input for strapping. Below are LED descriptions only.

Table 7. Port LED Pins

Pin Name Pin No. Type Drive (mA)Description LED_SPD[4:0]/… 93, I/OPU 4 Output After Reset = Used for 1st LED.

98, LEDMode[1:0]=11 -> Speed (On=100, Off=10) 104, LEDMode[1:0]=10 -> Speed (On=100, Off=10) 109, LEDMode[1:0]=01 -> Speed (On=100, Off=10) 114 LEDMode[1:0]=00 -> Reserved

Input Upon Reset = Refer to Table 9, on page 22, and Table 10, on page 24.

LED_ACT[4:0]/… 92, I/OPU 4 Output After Reset = Used for 2nd LED.

97, LEDMode[1:0]=11 -> Link/Act: (On=Link, Off=No Link,

Flash=Tx or Rx activity) 103,

LEDMode[1:0]=10 -> Act: (Off=No activity, On=Tx or Rx 108,

activity) 113

LEDMode[1:0]=01 -> RxAct: (Off=No activity, On=Rx activity) LEDMode[1:0]=00 -> Reserved

Input Upon Reset = Refer to Table 9, on page 22, and Table 10, on page 24.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

20 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Pin Name Pin No. Type Drive (mA)Description LED_DUP[4:0]/… 95, I/OPU 4 Output After Reset = Used for 3rd LED.

99, LEDMode[1:0]=11 -> Duplex/Col: (On=Full, Off=Half with no

collision, Flash=Collision) 105,

LEDMode[1:0]=10 -> Duplex/Col: (On=Full, Off=Half with no 110,

collision, Flash=Collision) 115

LEDMode[1:0]=01 -> TxAct: (Off=No activity, On=Tx activity) LEDMode[1:0]=00 -> Reserved

Input Upon Reset = Refer to Table 9, on page 22, and Table 10, on page 24.

LED_ADD[4:0]/.. 91, I/OPU 4 Output After Reset = Used for 4th LED.

96, LEDMode[1:0]=11 -> Link/Act/Spd: On for link established.

Blinking every 43ms when the corresponding port is transmitting 101,

or receiving at 100Mbps. Blinking every 120ms when the port is 107,

transmitting or receiving at 10Mbps. 111

LEDMode[1:0]=10 -> Bi-color Link/Active: polarity depends on Spd status.

LEDMode[1:0]=01 -> Link: (On=Link, Off=No Link) LEDMode[1:0]=00 -> Reserved

Input Upon Reset = Refer to Table 9, on page 22, and Table 10, on page 24.

LoopLED# 90 I/OPU 4 Output After Reset = LoopLED# used for LED. /EnDefer If the Loop detection function is enabled, this pin indicates

whether a Network loop is detected or not. Otherwise, this pin is of no use.

The LED statuses are represented as active-low or high depending on input strapping.

=> If Input=1: Output 0=Network loop is detected. 1=No loop. => If Input=0: Output 1=Network loop is detected. 0=No loop.

Input Upon Reset = Enable defer

1: Enable Carrier Sense Deferring function for half duplex back pressure.

0: Disable Carrier Sense Deferring function for half duplex back pressure.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 21 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 5.7. Serial EEPROM and SMI Pins As the output of the RTL8305SC is 3.3V, the serial EEPROM and external device must be 3.3V compatible.

Table 8. Serial EEPROM and SMI Pins

Pin Name Pin No. Type SCL_MDC 74 I/OPU

Drive (mA) Description

4 SCL or MDC

This pin is tri state when pin RESET#=0.

When pin EnEEPROM=1, this pin becomes SCL (output) to load the serial EEPROM upon reset. Then this pin changes to MDC (input) after reset.

When pin EnEEPROM=0, this pin is MDC (input): 0 to 25MHz clock, sourced by an external device to sample MDIO.

4 SDA or MDIO

This pin is tri state when RESET#=0.

When pin EnEEPROM=1, this pin becomes SDA (input/output) to load the serial EEPROM upon reset. Then this pin changes to MDIO (input/output) after reset. It should be pulled-high by an external resistor.

When pin EnEEPROM=0, this pin is MDIO (input/output). It should be pulled-high by an external resistor.

SDA_MDIO 75 I/OPU

5.8. Strapping Pins Pins that are dual function pins are outputs for LED or inputs for strapping. Below are strapping descriptions only.

Table 9. Strapping Pins

Pin Name Pin No. Type Drive (mA)Description EN_AUTOXOVER 69 IPU Enable Auto crossover function

1: Enable auto crossover detection

0: Disable auto crossover detection. MDI only

EN_RST_BLNK 71 IPU Enable Reset Blink

This enables blinking of the LEDs upon reset for diagnostic purposes.

1: Enable reset LED blinking 0: Disable reset LED blinking

DisTagPri 91 I/OPU 4 Input Upon Reset = Disable 802.1p VLAN Tag priority based

QoS function. /LED_ADD[4]

1: Disable 0: Enable

Output After Reset = Used for LED.

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RTL8305SC Datasheet Pin Name DISVLAN /LED_SPD[4]

Pin No. Type Drive (mA)Description 93 I/OPU 4 Input Upon Reset = Disable VLAN function

1: Disable VLAN

0: Enable VLAN. The default VLAN membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual VLANs. This default membership

configuration may be modified by setup internal registers via the SMI interface or EEPROM

Output After Reset = Used for LED.

97 I/OPU 4 Input Upon Reset = Enable 48 pass 1

1: 48 pass 1, continuously collides 48 input packets then passes 1 packet to retain system resource and avoid the partition in repeater when the packet buffer in 8305SC is full

0: Continuously collides to avoid packet loss when the packet buffer in 8305SC is full

Output After Reset = Used for LED.

98 I/OPU 4 Input Upon Reset = Disable ARP broadcast to all VLANs

1: Disables ability to broadcast ARP broadcast packets to all VLANs

0: Enables ability to broadcast ARP broadcast packets to all VLANs

ARP broadcast frame: DID is all F.

Output After Reset = Used for LED.

101 I/OPU 4 Input Upon Reset = Disable Leaky VLAN

1: Disable forwarding of unicast frames to other VLANs 0: Enable forwarding of unicast frames to other VLANs Broadcast and multicast frames adhere to the VLAN configuration.

Output After Reset = Used for LED.

111 I/OPU 4 Input Upon Reset = Enable to forward 802.1D specified reserved

multicast addresses frame

1: Forward reserved control frames, with DID=01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F

0: Filter reserved control packets, with DID=01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F

Output After Reset = Used for LED.

113 I/OPU 4 Input Upon Reset = Broadcast Input Drop

1: Use Broadcast Input drop mechanism 0: Use Broadcast Output drop mechanism

Output After Reset = Used for LED.

114 I/OPU 4 Input Upon Reset = Maximum Frame Length

1: 1536 Bytes 0: 1552 Bytes

Output After Reset = Used for LED.

23

Track ID: JATR-1076-21 Rev. 1.2

En48pass1 /LED_ACT[3]

DisARP

/LED_SPD[3]

DisLeaky

/LED_ADD[2]

EnForward /LED_ADD[0]

BCInDrop /LED_ACT[0]

Max1536 /LED_SPD[0]

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RTL8305SC Datasheet 5.9. Port Status Strapping Pins Pins that are dual function pins are outputs for LEDs or inputs for strapping. Below are strapping descriptions only.

Table 10. Port Status Strapping Pins

Pin Name SetGroup

/LED_DUP[4]

Pin No. Type Drive (mA)Description 95 I/OPU 4 Input Upon Reset = Set group of port 1

1: Port 0 is group X. Port 1, 2, and 3 are group Y

0: Port 0, and 1 are group X. Port 2, and 3 are group Y

Output After Reset = Used for LED.

GxMode 96 I/OPU 4 Input Upon Reset = Group X operating mode /LED_ADD[3] 1: UTP mode

0: FX mode

Output After Reset = Used for LED.

GyMode 99 I/OPU 4 Input Upon Reset = Group Y operating mode /LED_DUP[3] 1: UTP mode

0: FX mode

Output After Reset = Used for LED.

P4ANEG 103 I/OPU 4 Input Upon Reset = Port 4 Auto-Negotiation ability /LED_ACT[2] 1: Enable auto-negotiation (NWAY mode)

0: Disable auto-negotiation (Force mode)

Upon reset, this pin sets Reg.0.12 of Port 4. Strap after reset for initial value of Port 4 UTP mode only. This pin is not used for Port 4 FX, MAC mode MII, PHY mode MII, and PHY mode SNI.

Output After Reset = Used for LED.

GxANEG 104 I/OPU 4 Input Upon Reset = GroupX Auto-Negotiation ability /LED_SPD[2] 1: Enable auto-negotiation (NWAY mode)

0: Disable auto-negotiation (Force mode)

Upon reset, this pin sets Reg.0.12 of Group X. Strap after reset for initial value of UTP mode only. This pin is not used for FX.

Output After Reset = Used for LED.

GyANEG 105 I/OPU 4 Input Upon Reset = GroupY Auto-Negotiation ability /LED_DUP[2] 1: Enable auto-negotiation (NWAY mode)

0: Disable auto-negotiation (Force mode)

Upon reset, this pin sets Reg.0.12 of Group Y. Strap after reset for initial value of UTP mode only. This pin is not used for FX.

Output After Reset = Used for LED.

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RTL8305SC Datasheet Pin Name Pin No. Type Drive (mA)Description GxSpd100 107 I/OPU 4 Input Upon Reset = GroupX 10Base-T/100Base-TX ability /LED_ADD[1] GxSpd100=1, GxFull=1

=> MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 GxSpd100=1, GxFull=0

=> MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 GxSpd100=0, GxFull=1;

=> MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 GxSpd100=0, GxFull=0;

=> MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1

Upon reset, this pin sets Reg.0.13. In addition, upon reset, this pin and GxFull also sets Reg.4.8/4.7/4.6/4.5. Strap after reset for initial value of Group X UTP mode only. This pin is not used for FX.

Output After Reset = Used for LED.

GySpd100 108 I/OPU 4 Input Upon Reset = GroupY 10Base-T/100Base-TX ability /LED_ACT[1] GySpd100=1, GyFull=1

=> MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 GySpd100=1, GyFull=0

=> MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 GySpd100=0, GyFull=1;

=> MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 GySpd100=0, GyFull=0;

=> MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1

Upon reset, this pin sets Reg.0.13. In addition, upon reset, this pin and GyFull also sets Reg.4.8/4.7/4.6/4.5. Strap after reset for initial value of Group Y UTP mode only. This pin is not used for FX.

Output After Reset = Used for LED.

GxFull 109 I/OPU 4 Input Upon Reset = GroupX Full Duplex ability /LED_SPD[1] Upon reset, this pin sets the default value of Reg.0.8. In addition, on

reset, this pin also sets NWay full-duplex ability on Reg.4.8 and Reg.4.6. Strap after reset for initial value of Group X UTP or FX mode. FX can be Force 100 Full or Force 100 Half.

Output After Reset = Used for LED.

GyFull 110 I/OPU 4 Input Upon Reset = GroupY Full Duplex ability /LED_DUP[1] Upon reset, this pin sets the default value of Reg.0.8. On reset, this pin

also sets NWay full-duplex ability on Reg.4.8 and Reg.4.6.

Strap after reset for initial value of Group Y UTP or FX mode. FX can be Force 100 Full or Force 100 Half.

Output After Reset = Used for LED.

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RTL8305SC Datasheet 5.10. Power Pins Table 11. Power Pins

Pin Name AVDD18

Pin No. Type Drive (mA)Description

P 1.8V Analog Power 1, 7, 8, 14, 15,

21, 22, 28, 29, 35, 119, 128

HVDD33 118 P 3.3V Analog Power AGND P Analog Ground 4, 11, 18, 25,

32, 122, 126

DVDD18 43, 53, 70, 100 P 1.8V Digital Power DVDD33 62, 87, 106 P 3.3V Digital Power DGND P Digital Ground 39, 50, 64, 79,

94, 102, 112

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RTL8305SC Datasheet 6. EEPROM Description

6.1. Port 0 Registers 6.1.1. Global Control Register0

Table 12. Global Control Register0

Name Byte.bitDescription EEPROM Existence 0.7 1: EEPROM does not exist (pin EnEEPROM=0 or pin EnEEPROM=1 but

EEPROM does not exist)

0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists)

Reserved 0.6 Internal Use 0.5 Internal Use 0.4 Internal Use 0.3

0.2 1: Enable loop detection function Enable Loop

Detection Function 0: Disable loop detection function Reserved 0.1 Internal Use 0.0

Default

0

1 1 1 1 0 1 0

6.1.2. Global Control Register1

Table 13. Global Control Register1

Name

Page selection

Description

1: Select the registers in page 1 0: Select the registers in page 0

Reserved 1.6

1.5 1: Lookup table is accessible via indirect access registers Lookup table

accessible enable 0: Lookup table is not accessible Internal Use 1.4

Reserved 1.3

1.2 Disable 802.1Q 1: Disable 802.1Q tagged-VID Aware function. The RTL8305SC will not

tag aware VLAN check the tagged VID on received frames to perform tagged-VID VLAN

mapping. Under this configuration, the RTL8305SC only uses the per port VLAN index register to perform Port-Based VLAN mapping

0: Enable the Member Set Filtering function of VLAN Ingress Rule. The RTL8305SC checks the tagged VID on received frames with the

VIDA[11:0]~VIDH[11:0] to index to a member set, then performs VLAN mapping. The RTL8305SC uses tagged-VID VLAN mapping for tagged frames but still uses Port-Based VLAN mapping for priority-tagged and untagged frames

Byte.bit 1.7

Default 0 0 0 0 0 1

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RTL8305SC Datasheet Name

Disable VLAN member set ingress filtering

Byte.bit 1.1

Description Default

1 1: The switch will not drop the received frame if the ingress port of this

packet is not included in the matched VLAN member set. It will still forward the packet to the VLAN members specified in the matched member set. This setting works on both port-based and tag-based VLAN configurations

0: The switch will drop the received frame if the ingress port of this packet is not included in the matched VLAN member set

1: The switch accepts all frames it receives whether tagged or untagged. 1 0: The switch will only accept tagged frames and will drop untagged frames.

Disable VLAN tag admit control

1.0

6.1.3. Global Control Register2

Table 14. Global Control Register2

Name

Internal Use Internal Use Internal Use

Byte.bit 2.7 2.6 2.5~2.0

Description

Default 0 0 11 1111

6.1.4. Global Control Register3

Table 15. Global Control Register3

Name

Internal Use Internal Use Internal Use

Byte.bit 3.7 3.6 3.5~3.0

Description

Default 0 0 11 1111

6.1.5. Global Control Register4

Table 16. Global Control Register4

Name Byte.bit Description

Reserved 4.7 Enable defer 4.6 1: Enable carrier sense deferring for half duplex back pressure

Default

1 1 1 11

0: Disable carrier sense deferring for half duplex back pressure

LED blink time Queue weight

4.5 4.4~4.3

1: On 43ms, then Off 43ms 0: On 120ms, then Off 120ms

The frame service ratio between the high priority queue and low priority queue is: 11=16:1

10=Always high priority queue first 01=8:1 00=4:1

1: Disable Broadcast Storm Control 0: Enable Broadcast Storm Control

28

Disable broadcast storm control

4.2 1

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RTL8305SC Datasheet Name Byte.bit Description

4.1 1: Enable power-on LED blinking for diagnosis Enable power-on

blinking 0: Disable power-on LED blinking for diagnosis Reserved 4.0

Default

1 1

6.1.6. Global Control Register5

Table 17. Global Control Register5

Name Byte.bit Description Default Reserved 5.7 1

5.6 1: 1536 Byte 1 Maximum Frame

Length 0: 1552 Byte

5.5 1: Use Broadcast Input drop mechanism 1 Enable broadcast

drop 0: Use Broadcast Output drop mechanism

5.4 1 Forward 802.1D 1: Forward reserved control frames, which DID=01-80-C2-00-00-02 and 01-reserved MAC 80-C2-00-00-04 to 01-80-C2-00-00-0F packets

addresses frame. 0: Filter reserved control packets, which DID=01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F

5.3 1: Disable forwarding of unicast frames to other VLANs 1 Disable leaky

VLAN 0: Enable forwarding of unicast frames to other VLANs

Broadcast and multicast frames adhere to the VLAN configuration.

5.2 1: Disable to broadcast the ARP broadcast packet to all VLANs 1 Disable ARP

VLAN 0: Enable to broadcast the ARP broadcast packet to all VLANs

ARP broadcast frame: DID is all F.

Enable 48 pass 1 5.1 1 1: 48 pass 1, continuously collides 48 input packets then passes 1 packet to

retain system resource and avoid partition in the repeater when the packet buffer is full

0: Continuously collides to avoid packet loss when the packet buffer is full

Disable VLAN 5.0 1: Disable VLAN 1

0: Enable VLAN. The default VLAN membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual VLANs. This default membership configuration may be modified by setup internal registers via the SMI interface or EEPROM

6.1.7. Global Control Register6

Table 18. Global Control Register6

Name Byte.bit Description Reserved 6.7~6.0

Default

1111 1111

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RTL8305SC Datasheet 6.1.8. Global Control Register7

Table 19. Global Control Register 7

Name Byte.bit Description Reserved 7.7~7.6 LED Mode[1:0] 7.5~7.4 11=Mode 3: Speed, Link+Act, Duplex+Col, Link/Act/Speed

10=Mode 2: Speed, Act, Duplex/Col, Bi-color Link/Activity 01=Mode 1: Speed, RxAct, TxAct, Link 00=Mode 0: Reserved

Internal Use 7.3

7.2 Disable dual MII 1: Disable dual MII interface of port 4. Only provides MII interface for the

interface of port 4 MAC circuit of port 4

0: Enable dual MII interface of port 4. Not only provides MII interface for the MAC circuit of port 4 but provides MII interface for the PHY circuit of port 4

Reserved 7.1~7.0

Default

11 11

1 1

11

6.1.9. Port 0 Control 0

Table 20. Port 0 Control 0

Name Byte.bit Description Reserved 8.7 Internal Use 8.6 Internal Use 8.5~8.4 Internal Use 8.3 Internal Use 8.2

8.1~8.0 For port 0 egress packets VLAN tag insert

and remove 11=Do not insert or remove VLAN tags to/from packet

10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets

Default 0 1 11 1 1 11

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RTL8305SC Datasheet 6.1.10. Port 0 Control 1

Table 21. Port 0 Control 1

Name Byte.bit Description Default Reserved 9.7 1 Internal Use 9.6 0 Local loopback 9.5 1: Perform ‘local loopback’, i.e. loopback MAC’s RX back to TX 0

0: Normal operation

Internal Use 9.4 0

9.3 0 Discard Non 1: If the received packets are tagged, the switch will discard packets whose

PVID packets VID does not match the ingress port’s PVID

0: No packets will be dropped

9.2 1: Disable 802.1p priority classification for ingress packets on port 0 1 Disable 802.1p

priority 0: Enable 802.1p priority classification on port 0

9.1 1: Disable Diffserv priority classification for ingress packets on port 0 1 Disable Diffserv

priority 0: Enable Diffserv priority classification

9.0 1: Disable port based priority QoS function on port 0 1 Disable port-based priority on 0: Enable port based priority QoS function on port 0. Ingress packets on port

port 0 0 will be classed as high priority

6.1.11. Port 0 Control 2

Table 22. Port 0 Control 2

Name Byte.bit Description Reserved 10.7~10.0

Default

0000 0000

6.1.12. Port 0 Control 3

Table 23. Port 0 Control 3

Name Byte.bit Description Reserved 11.7~11.0

Default

0000 0000

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RTL8305SC Datasheet 6.1.13. Port 0 Control 4 & VLAN Entry [A]

Table 24. Port 0 Control 4 & VLAN Entry [A]

Name

Byte.bit

Description

VLAN Entry [A]

12.7 Internal Use 12.6 Internal Use

Reserved 12.5

12.4~12.0 This 5-bit field specifies which ports are the members of VLAN A. If a VLAN ID [A]

membership Bit destination address look up fails, the packet associated with this VLAN will [4:0] be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN A 10010 means port 4 and 1 are the members of VLAN A 11111 means all 5 ports are the members of VLAN A

Port 0 Control 4

13.7~13.5 In a port-based VLAN configuration, this register indexes port 0’s ‘Port Port 0 VLAN

index [3:0] VLAN Membership’, which can be defined in one of the registers ‘VLAN

ID [A] Membership’ to “VLAN ID [P] Membership”. Port 0 can only

communicate within the membership. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

Internal Use 13.3 Internal Use 13.2 Internal Use 13.1

Reserved 13.0

VLAN Entry [A]

14.7~14.0 This register along with byte 15.3~15.0 defines the IEEE 802.1Q 12-bit VLAN ID [A]

[7:0] VLAN identifier of VLAN A

Port 0 Control 4 & VLAN Entry [A]

Internal Use Internal Use Internal Use Internal Use VLAN ID [A] [11:8]

15.7 15.6 15.5 15.4 15.3~15.0

This register along with byte 14.7~14.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A

1 1 1 1 0000 1

1

0 1 0001 Default

0000

1 1 1 0 0000 0000

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RTL8305SC Datasheet 6.2. Port 1 Registers 6.2.1. Internal Use Register

Table 25. Internal Use Register

Name

Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use

Byte.bit Description 16.7~16.0 Internal Use 17.7~17.0 Internal Use 18.7~18.0 Internal Use 19.7~19.0 Internal Use 20.7~20.0 Internal Use 21.7~21.0 Internal Use 22.7~22.0 Internal Use 23.7~23.0 Internal Use

Default

0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

6.2.2. Port 1 Control 0

Table 26. Port 1 Control 0

Name Byte.bit Description Reserved 24.7 Internal Use 24.6 Internal Use 24.5~24.4 Internal Use 24.3 Internal Use 24.2

VLAN tag insert 24.1~24.0 For port 1 egress packets and remove 11=Do not insert or remove VLAN tags to/from packet

10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets

Default 0 1 11 1 1 11

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RTL8305SC Datasheet 6.2.3. Port 1 Control 1

Table 27. Port 1 Control 1

Name Byte.bit Description Default Reserved 25.7 1 Internal Use 25.6 0 Local loopback 25.5 1: Perform local loopback, i.e. loopback MAC’s RX back to TX 0

0: Normal operation

Internal Use 25.4 0

25.3 1: If the received packets are tagged, the switch will discard packets whose VID 0 Discard Non

PVID packets does not match the ingress port’s PVID

0: No packets will be dropped

25.2 1: Disable 802.1p priority classification for ingress packets on port 1 1 Disable 802.1p

priority 0: Enable 802.1p priority classification on port 1

25.1 1: Disable Diffserv priority classification for ingress packets on port 1 1 Disable Diffserv

priority 0: Enable Diffserv priority classification

25.0 1: Disable port based priority QoS function on port 1 1 Disable port-based priority on 0: Enable port-based priority QoS function on port 1. Ingress packets on port 1

port 1 will be classed as high priority

6.2.4. Port 1 Control 2

Table 28. Port 1 Control 2

Name Byte.bit Description Default Internal Use 26.7 0 Reserved 26.6~ 26.5 10 Internal Use 26.4 1 Reserved 26.3~ 26.0 1111

6.2.5. Port 1 Control 3

Table 29. Port 1 Control 2

Name Byte.bit Description Default Reserved 27.7 1 Internal Use 27.6 0 Reserved 27.5~ 00 1111 27.0

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RTL8305SC Datasheet 6.2.6. Port 1 Control 4 & VLAN Entry [B]

Table 30. Port 1 Control 4 & VLAN Entry [B]

Name

Byte.bit Description

VLAN Entry [B]

1 28.7 Internal Use

28.6 1 Internal Use

Reserved 28.5 0

28.4~ This 5-bit field specifies which ports are the members of VLAN B. If a 1 0010 VLAN ID [B]

Membership Bit 28.0 destination address look up fails, the packet associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN B 10010 means port 4 and 1 are the members of VLAN B 11111 means all 5 ports are members of VLAN B.

Port 1 Control 4

29.7~ In a port-based VLAN configuration, this register indexes to port 1’s ‘Port 0001 Port 1 VLAN

index [3:0] 29.5 VLAN Membership’, which may be defined in one of the registers ‘VLAN ID

[A] Membership’ to ‘VLAN ID [P] Membership’. Port 1 can only communicate with members within this VLAN. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0001, which indexes to the VLAN entry [B] that is composed of VLAN ID [B] Membership Bit [4:0] in PHY1 Reg.24.[4:0] and VLAN ID [B] in PHY1 Reg.25.[11:0].

Internal Use 29.3 1 Internal Use 29.2 1 Internal Use 29.1 1 Reserved 29.0 0

VLAN Entry [B]

30.7~ This register, along with byte 31.3~31.0, defines the IEEE 802.1Q 12-bit VLAN 0000 VLAN ID [B]

[7:0] 30.0 identifier of VLAN B. 0001

Port 1 Control 4 & VLAN Entry [B]

Internal Use 31.7 1 Internal Use 31.6 1

1 Internal Use 31.5

Internal Use 31.4 1

31.3~ This register, along with byte 30.7~30.0, defines the IEEE 802.1Q 12-bit VLAN 0000 VLAN ID [B]

[11:8] 31.0 identifier of VLAN B.

Default

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RTL8305SC Datasheet 6.3. Port 2 Registers 6.3.1. Internal Use Register

Table 31. Internal Use Register

Name Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use

Description

Internal Use Register

32.7~32.0 33.7~33.0 34.7~34.0 35.7~35.0 36.7~36.0 37.7~37.0 38.7~38.0 39.7~39.0 Byte.bit

Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF

6.3.2. Port 2 Control 0

Table 32. Port 2 Control 0

Name Byte.bit Description Reserved 40.7 Internal Use 40.6 Internal Use 40.5~40.4 Internal Use 40.3 Internal Use 40.2

VLAN tag insert 40.1~40.0 For port 2 egress packets and remove 11=Do not insert or remove VLAN tags to/from packet

10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets

Default 0 1 11 1 1 11

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RTL8305SC Datasheet 6.3.3. Port 2 Control 1

Table 33. Port 2 Control 1

Name Byte.bit Description Reserved 41.7 Internal Use 41.6 Local loopback 41.5 1: Perform ‘local loopback’, i.e. loopback MAC’s RX back to TX

0: Normal operation

Internal Use 41.4

41.3 Discard Non 1: If the received packets are tagged, the switch will discard packets whose

PVID packets VID does not match the ingress port’s PVID

0: No packets will be dropped

41.2 1: Disable 802.1p priority classification for ingress packets on port 2 Disable 802.1p

priority 0: Enable 802.1p priority classification on port 2

41.1 1: Disable Diffserv priority classification for ingress packets on port 2 Disable Diffserv

priority 0: Enable Diffserv priority classification

41.0 1: Disable port based priority QoS function on port 2 Disable port-based priority on 0: Enable port based priority QoS function on port 2. Ingress packets on

port 2 port 2 will be classed as high priority

Default

1 0 0 0 0

1 1 1

6.3.4. Reserved

Table 34. Reserved

Name Byte.bit Description Reserved 42.7~42.0 Reserved 43.7~43.0

Default

0x20 0x00

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RTL8305SC Datasheet 6.3.5. Port 2 Control 2 & VLAN Entry [C]

Table 35. Port 2 Control 2 & VLAN Entry [C]

Name

Byte.bit Description

VLAN Entry [C]

Internal Use 44.7 Internal Use 44.6

Reserved 44.5 VLAN ID [C] 44.4~44.This 5-bit field specifies which ports are the members of VLAN C. If a Membership Bit 0 destination address look up fails, the packet associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.

10001 means port 4 and 0 are the members of VLAN C 10010 means port 4 and 1 are the members of VLAN C 11111 means all 5 ports are the members of VLAN C

Port 2 Control 2

Port 2 VLAN 45.7~45.In a port-based VLAN configuration, this register indexes to port 2’s ‘Port index [3:0] 5 VLAN Membership’, which can be defined in one of the registers ‘VLAN ID

[A] Membership’ to ‘VLAN ID [P] Membership’. Port 2 can only communicate with members within this VLAN. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0010, which indexes to the VLAN entry [C] that is composed of VLAN ID [C] Membership Bit [4:0] in PHY2 Reg.24.[4:0] and VLAN ID [C] in PHY2 Reg.25.[11:0].

Internal Use 45.3 Internal Use 45.2 Internal Use 45.1

Reserved 45.0

VLAN Entry [C]

VLAN ID [C] 46.7~46.This register along with byte 47.3~47.0 defines the IEEE 802.1Q 12-bit VLAN [7:0] 0 identifier of VLAN C

Port 2 Control 2 & VLAN Entry [C]

Internal Use Internal Use Internal Use Internal Use VLAN ID [C] [11:8]

47.7 47.6 47.5 47.4 47.3~47.

0

This register along with byte 46.7~46.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C

1 1 1 1 0000 1 1 0 1 0100 Default

0010

1 1 1 0 0000 0010

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RTL8305SC Datasheet 6.4. Port 3 Registers 6.4.1. Switch MAC Address

The Switch MAC address is used as the source address in MAC pause control frames.

Table 36. Switch MAC Address

Name

Switch MAC Address [47:40] Switch MAC Address [39:32] Switch MAC Address [31:24] Switch MAC Address [23:16] Switch MAC Address [15:8] Switch MAC Address [7:0]

Byte.bit Description

48.7~48.0 Switch MAC Address Byte 5 49.7~49.0 Switch MAC Address Byte 4 50.7~50.0 Switch MAC Address Byte 3 51.7~51.0 Switch MAC Address Byte 2 52.7~52.0 Switch MAC Address Byte 1 53.7~53.0 Switch MAC Address Byte 0

Default0x52 0x54 0x4C 0x83 0x05 0xC0

6.4.2. Port 3 Control 0

Table 37. Port 3 Control 0

Name Byte.bit Description Reserved 54.7 Internal Use 54.6 Internal Use 54.5~54.4 Internal Use 54.3 Internal Use 54.2

VLAN tag insert 54.1~54.0 For port 3 egress packets and remove 11=Do not insert or remove VLAN tags to/from packet

10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets

Default

0 1 11 1 1 11

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RTL8305SC Datasheet 6.4.3. Port 3 Control 1

Table 38. Port 3 Control 1

Name Byte.bit Description Reserved 55.7 Internal Use 55.6 Local loopback 55.5 1: Perform ‘local loopback’, i.e. loopback MAC’s RX back to TX

0: Normal operation

Internal Use 55.4

55.3 Discard Non PVID 1: If the received packets are tagged, the switch will discard packets whose

packets VID does not match the ingress port’s PVID

0: No packets will be dropped

55.2 1: Disable 802.1p priority classification for ingress packets on port 3 Disable 802.1p

priority 0: Enable 802.1p priority classification on port 3

55.1 1: Disable Diffserv priority classification for ingress packets on port 3 Disable Diffserv

priority 0: Enable Diffserv priority classification

55.0 1: Disable port-based priority QoS function on port 3 Disable port-based

priority on port 3 0: Enable port-based priority QoS function on port 3. Ingress packets on

port 3 will be classed as high priority

Default 1 0 0 0 0

1 1 1

6.4.4. Reserved

Table 39. Reserved

Name Byte.bit Description Reserved 56.7~56.0 Reserved 57.7~57.0

Default

0x00 0x00

6.4.5. Port 3 Control 2 & VLAN Entry [D]

Table 40. Port 3 Control 2 & VLAN Entry [D]

Name

Byte.bit

Description

VLAN Entry [D]

Internal Use 58.7 1 Internal Use 58.6 1 Reserved 58.5 0

58.4~58.0 This 5-bit field specifies which ports are the members of VLAN D. If a 1 1000 VLAN ID [D]

Membership Bit destination address look up fails, the packet associated with this VLAN will [4:0] be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN D 10010 means port 4 and 1 are the members of VLAN D 11111 means all 5 ports are the members of VLAN D

Default

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RTL8305SC Datasheet Port 3 Control 2

59.7~59.5 In a port-based VLAN configuration, this register indexes to port 3’s ‘Port Port 3 VLAN

index [3:0] VLAN Membership’, which can be defined in one of the registers ‘VLAN

ID [A] Membership’ to ‘VLAN ID [P] Membership’. Port 3 can only communicate with the members within this VLAN. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID. The default value of this register is 0011, which indexes to the VLAN entry [D] that is composed of VLAN ID [D] Membership Bit [4:0] in PHY3 Reg.24.[4:0] and VLAN ID [D] in PHY3 Reg.25.[11:0].

Internal Use 59.3 Internal Use 59.2 Internal Use 59.1

Reserved 59.0

VLAN Entry [D]

60.7~60.0 This register along with byte 61.3~61.0 defines the IEEE 802.1Q 12-bit VLAN ID [D]

[7:0] VLAN identifier of VLAN D

Port 3 Control 2 & VLAN Entry [D]

Internal Use Internal Use Internal Use Internal Use VLAN ID [D] [11:8]

61.7 61.6 61.5 61.4 61.3~61.0

This register along with byte 60.7~60.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D

1 1 1 1 0000 0011

1 1 1 0 0000 0011

6.4.6. Internal Use Register

Table 41. Internal Use Register

Name

Internal Use Internal Use Internal Use Internal Use Internal Use Internal Use

Byte.bit 62.7~62.0 63.7~63.0 64.7~64.0 65.7~65.0 66.7~66.0 67.7~67.0

Description

Default 0x00 0x00 0x00 0x00 0x00 0x00

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RTL8305SC Datasheet 6.5. Port 4 Registers 6.5.1. Port 4 Control 0

Table 42. Port 4 Control 0

Name Byte.bit Description Reserved 68.7 Internal Use 68.6 Internal Use 68.5~68.4 Internal Use 68.3 Internal Use 68.2

68.1~68.0 For port 4 egress packets VLAN tag insert

and remove 11=Do not insert or remove VLAN tags to/from packet

10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets

00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets

Default 0 1 11 1 1 11

6.5.2. Port 4 Control 1

Table 43. Port 4 Control 1

Name Byte.bit Description Default Reserved 69.7 1 Internal Use 69.6 0 Local loopback 69.5 1: Perform ‘local loopback’, i.e. loopback MAC’s RX back to TX 0

0: Normal operation

Internal Use 69.4 0

69.3 0 Discard Non 1: If the received packets are tagged, the switch will discard packets whose

PVID packets VID does not match the ingress port’s PVID

0: No packets will be dropped

69.2 1: Disable 802.1p priority classification for ingress packets on port 4 1 Disable 802.1p

priority 0: Enable 802.1p priority classification on port 4

69.1 1: Disable Diffserv priority classification for ingress packets on port 4 1 Disable Diffserv

priority 0: Enable Diffserv priority classification

69.0 1: Disable port based priority QoS function on port 4 1 Disable port-based priority on 0: Enable port based priority QoS function on port 4. Ingress packet on port

port 4 4 will be classified as high priority

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RTL8305SC Datasheet 6.5.3. Reserved

Table 44. Reserved

Name Byte.bit Description Reserved 70.7~70.0 Reserved 71.7~71.0

Default

0x00 0x00

6.5.4. Port 4 Control 2 & VLAN Entry [E]

Table 45. Port 4 Control 2 & VLAN Entry [E]

Name

Byte.bit

Description

VLAN Entry [E]

Internal Use 72.7 Internal Use 72.6

Reserved 72.5

72.4~72.0 This 5-bit field specifies which ports are the members of VLAN E. If a VLAN ID [E]

Membership Bit destination address look up fails, a packet associated with this VLAN will [4:0] be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN E 10010 means port 4 and 1 are the members of VLAN E 11111 means all 5 ports are the members of VLAN E

Port 4 Control 2

73.7~73.5 In a port-based VLAN configuration, this register indexes to port 4’s ‘Port Port 4 VLAN

index [3:0] VLAN Membership’, which can be defined in one of the registers ‘VLAN

ID [A] Membership’ to ‘VLAN ID [P] Membership’. Port 4 can only communicate with the members within this VLAN. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID. The default value of this register is 0100, which indexes to the VLAN entry [E] that is composed of VLAN ID [E] Membership Bit [4:0] in PHY4 Reg.24.[4:0] and VLAN ID [E] in PHY4 Reg.25.[11:0].

Internal Use 73.3 Internal Use 73.2 Internal Use 73.1

Reserved 73.0

VLAN Entry [E]

74.7~74.0 This register, along with byte 75.3~75.0, defines the IEEE 802.1Q 12-bit VLAN ID [E]

[7:0] VLAN identifier of VLAN E

Port 4 Control 2 & VLAN Entry [E]

Internal Use Internal Use Internal Use Internal Use VLAN ID [E] [11:8]

75.7 75.6 75.5 75.4 75.3~75.0

This register, along with byte 74.7~74.0, defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E

43

1 1 1 1 0000 1 1 0 1 1111 Default

0100

1 1 1 0 0000 0100

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RTL8305SC Datasheet 6.5.5. Internal Use Register

Table 46. Internal Use Register

Name Byte.bit Description Reserved 76.7 Internal Use 76.6~76.4 Reserved 76.3 Internal Use 76.2~76.0

Default

0 100 0 000

6.5.6. 802.1p Base Priority

Table 47. 802.1p Base Priority

Name

802.1p base priority

Description

Classifies priority for incoming 802.1Q packets, if 802.1p priority classification is enabled. “User priority” compared against this value. >=: Classify as high priority <: Classify as low priority

Reserved 77.4~77.0

Byte.bit

77.7~77.5

Default 100

0 0000

6.6. VLAN Entries 6.6.1. VLAN Entry [F]

Table 48. VLAN Entry [F]

Name

Byte.bit

Description

VLAN Entry [F]

Reserved 78.7~78.5

78.4~78.0 This 5-bit field specifies which ports are the members of VLAN F. If a VLAN ID [F]

Membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN F 10010 means port 4 and 1 are the members of VLAN F 11111 means all 5 ports are the members of VLAN F

Reserved 79.7~79.0 80.7~80.0 This register along with byte 81.3~81.0 defines the IEEE 802.1Q 12-bit VLAN ID [F] [7:0] VLAN identifier of VLAN F Reserved 81.7~81.4

81.3~81.0 This register along with byte 80.7~80.0 defines the IEEE 802.1Q 12-bit VLAN ID [F]

[11:8] VLAN identifier of VLAN F

000

1 0001 Default

0101 0000 0000 0101 1111 0000

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RTL8305SC Datasheet 6.6.2. VLAN Entry [G]

Table 49. VLAN Entry [G]

Name

Byte.bit Description

VLAN Entry [G]

Reserved 82.7~82.5

82.4~82.0 This 5-bit field specifies which ports are the members of VLAN G. If a VLAN ID [G]

membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN G 10010 means port 4 and 1 are the members of VLAN G 11111 means all 5 ports are the members of VLAN G

Reserved 83.7~83.0 84.7~84.0 This register along with byte 85.3~85.0 defines the IEEE 802.1Q 12-bit VLAN ID [G] [7:0] VLAN identifier of VLAN G Reserved 85.7~85.4

85.3~85.0 This register along with byte 84.7~84.0 defines the IEEE 802.1Q 12-bit VLAN ID [G]

[11:8] VLAN identifier of VLAN G

000

1 0010 Default

0110 0000 0000 0110 1111 0000

6.6.3. VLAN Entry [H]

Table 50. VLAN Entry [H]

Name

Byte.bit Description

VLAN Entry [H]

Reserved 86.7~86.5

VLAN ID [H] 86.4~86.0 This 5-bit field specifies which ports are the members of VLAN H. If a membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN H 10010 means port 4 and 1 are the members of VLAN H 11111 means all 5 ports are members of VLAN H

Reserved 87.7~87.0 VLAN ID [H] 88.7~88.0 This register along with byte 89.3~89.0 defines the IEEE 802.1Q 12-bit VLAN [7:0] identifier of VLAN H Reserved 89.7~89.4

VLAN ID [H] 89.3~89.0 This register along with byte 88.7~88.0 defines the IEEE 802.1Q 12-bit VLAN [11:8] identifier of VLAN H

000

1 0100 Default

0111 0000 0000 0111 1111 0000

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RTL8305SC Datasheet 6.6.4. VLAN Entry [I]

Table 51. VLAN Entry [I]

Name

Byte.bit

Description

VLAN Entry [I]

Reserved 90.7~90.5

90.4~90.0 This 5-bit field specifies which ports are the members of VLAN I. If a VLAN ID [I]

membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN I 10010 means port 4 and 1 are the members of VLAN I 11111 means all 5 ports are the members of VLAN I

Reserved 91.7~91.0 92.7~92.0 This register along with byte 93.3~93.0 defines the IEEE 802.1Q 12-bit VLAN VLAN ID [I] [7:0] identifier of VLAN I Reserved 93.7~93.4

93.3~93.0 This register along with byte 92.7~92.0 defines the IEEE 802.1Q 12-bit VLAN VLAN ID [I]

[11:8] identifier of VLAN I

000

1 1000 Default

1000 0000 0000 1000 1111 0000

6.6.5. VLAN Entry [J]

Table 52. VLAN Entry [J]

Name

Byte.bit

Description

VLAN Entry [I]

Reserved 94.7~94.5

94.4~94.0 This 5-bit field specifies which ports are the members of VLAN J. If a VLAN ID [J]

membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN J 10010 means port 4 and 1 are the members of VLAN J 11111 means all 5 ports are members of VLAN J

Reserved 95.7~95.0 96.7~96.0 This register along with byte 97.3~97.0 defines the IEEE 802.1Q 12-bit VLAN VLAN ID [J] [7:0] identifier of VLAN J Reserved 97.7~97.4

97.3~97.0 This register along with byte 96.7~96.0 defines the IEEE 802.1Q 12-bit VLAN VLAN ID [J]

[11:8] identifier of VLAN J

000

1 1111 Default

1001 0000 0000 1001 1111 0000

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RTL8305SC Datasheet 6.6.6. VLAN Entry [K]

Table 53. VLAN Entry [K]

Name Byte.bit Description Default Reserved 98.7~98.5 000

98.4~98.0 This 5-bit field specifies which ports are the members of VLAN K. If a 1 0001 VLAN ID [K]

Membership destination address look up fails, the packet associated with this VLAN will be Bit [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands

for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN K 10010 means port 4 and 1 are the members of VLAN K 11111 means all 5 ports are the members of VLAN K

Reserved 99.7~99.0 1010

0000 0000 VLAN ID [K] 100.7~100.This register along with byte 101.3~101.0 defines the IEEE 802.1Q 12-bit

[7:0] 0 VLAN identifier of VLAN K 1010 Reserved 1111 101.7~101.

4

0000 VLAN ID [K] 101.3~101.This register along with byte 100.7~100.0 defines the IEEE 802.1Q 12-bit

[11:8] 0 VLAN identifier of VLAN K

6.6.7. VLAN Entry [L]

Table 54. VLAN Entry [L]

Name

Byte.bit

Description

VLAN Entry [L]

Reserved 102.7~102.5

102.4~102.0 This 5-bit field specifies which ports are the members of VLAN L. If a VLAN ID [L]

membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN L 10010 means port 4 and 1 are the members of VLAN L 11111 means all 5 ports are members of VLAN L

Reserved 103.7~103.0 104.7~104.0 This register along with byte 105.3~105.0 defines the IEEE 802.1Q 12-bit VLAN ID [L] [7:0] VLAN identifier of VLAN L Reserved 105.7~105.4

105.3~105.0 This register along with byte 104.7~104.0 defines the IEEE 802.1Q 12-bit VLAN ID [L]

[11:8] VLAN identifier of VLAN L

000

1 0010 Default

1011 0000 0000 1011 1111 0000

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RTL8305SC Datasheet 6.6.8. VLAN Entry [M]

Table 55. VLAN Entry [M]

Name

Byte.bit

Description

VLAN Entry [M]

Reserved 106.7~106.5

VLAN ID [M] 106.4~106.0 This 5-bit field specifies which ports are the members of VLAN M. If a membership Bit destination address look up fails, the packet associated with this VLAN will [4:0] be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN M 10010 means port 4 and 1 are the members of VLAN M 11111 means all 5 ports are members of VLAN M

Reserved 107.7~107.0 VLAN ID [M] 108.7~108.0 This register along with byte 109.3~109.0 defines the IEEE 802.1Q 12-bit [7:0] VLAN identifier of VLAN M Reserved 109.7~109.4

VLAN ID [M] 109.3~109.0 This register along with byte 108.7~108.0 defines the IEEE 802.1Q 12-bit [11:8] VLAN identifier of VLAN M

000

1 0100 Default

1100 0000 0000 1100 1111 0000

6.6.9. VLAN Entry [N]

Table 56. VLAN Entry [N]

Name

Byte.bit

Description

VLAN Entry [N]

Reserved 110.7~110.5

VLAN ID [N] 110.4~110.0 This 5-bit field specifies which ports are the members of VLAN N. If a membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN N 10010 means port 4 and 1 are the members of VLAN N 11111 means all 5 ports are the members of VLAN N

Reserved 111.7~111.0 VLAN ID [N] 112.7~112.0 This register along with byte 113.3~113.0 defines the IEEE 802.1Q 12-bit [7:0] VLAN identifier of VLAN N Reserved 113.7~113.4

VLAN ID [N] 113.3~113.0 This register along with byte 112.7~112.0 defines the IEEE 802.1Q 12-bit [11:8] VLAN identifier of VLAN M

000

1 1000 Default

1101 0000 0000 1101 1111 0000

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RTL8305SC Datasheet 6.6.10. VLAN Entry [O]

Table 57. VLAN Entry [O]

Name

Byte.bit

Description

VLAN Entry [O]

Reserved 114.7~114.5

VLAN ID [O] 114.4~114.0 This 5-bit field specifies which ports are the members of VLAN O. If a membership Bit destination address look up fails, packets associated with this VLAN will be [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN O 10010 means port 4 and 1 are the members of VLAN O 11111 means all 5 ports are members of VLAN O

Reserved 115.7~115.0 VLAN ID [O] 116.7~116.0 This register along with byte 117.3~117.0 defines the IEEE 802.1Q 12-bit [7:0] VLAN identifier of VLAN O Reserved 117.7~117.4

VLAN ID [O] 117.3~117.0 This register along with byte 116.7~116.0 defines the IEEE 802.1Q 12-bit [11:8] VLAN identifier of VLAN O

000

1 1111 Default

1110 0000 0000 1110 1111 0000

6.6.11. VLAN Entry [P]

Table 58. VLAN Entry [P]

Name

Byte.bit

Description

VLAN Entry [P]

Reserved 118.7~118.5

118.4~118.0 This 5-bit field specifies which ports are the members of VLAN P. If a VLAN ID [P]

Membership destination address look up fails, packets associated with this VLAN will be Bit [4:0] broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4

stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN P 10010 means port 4 and 1 are the members of VLAN P 11111 means all 5 ports are members of VLAN P

Reserved 119.7~119.0 120.7~120.0 This register along with byte 27.3~27.0 defines the IEEE 802.1Q 12-bit VLAN ID [P] [7:0] VLAN identifier of VLAN P Reserved 121.7~121.4

121.3~121.0 This register along with byte 26.7~26.0 defines the IEEE 802.1Q 12-bit VLAN ID [P]

[11:8] VLAN identifier of VLAN P

000

1 0001 Default

1111 0000 0000 1111 1111 0000

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RTL8305SC Datasheet 7. Register Descriptions

Hardware Reset: pin RESET#=0 to 1. Reset all then load EEPROM and Pin registers with serial EEPROM and Pin strapping.

Soft Reset: Write bit12 of Reg16 of PHY0 as 1. Reset all except loading EEPROM and Pin Registers with serial EEPROM and Pins. After updating the EEPROM or Pin registers via SMI, the external device must do a soft reset in order to allow the configuration change to take affect. Note: In this section the following abbreviations are used:

RO: Read Only RW: Read/Write

LL: Latch Low until clear

Table 59. Register Descriptions

Name

Port 0 PHY Register

PHY 0

Register Register Description 0 Control Register 1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 16~19 Global Control Register 22 Port 0 Control Register 0 24 Port 0 Control Register 1 & VLAN ID [A] Membership 25 Port 0 Control Register 2 & VLAN ID [A]

0 26 Reserved 1 26 VLAN ID [F] Membership 0 27 Reserved 1 27 VLAN ID [F] 0 28 Reserved 1 28 VLAN ID [K] Membership 0 29 Reserved 1 29 VLAN ID [K] 0 30 Reserved 1 30 VLAN ID [P] Membership 0 31 Reserved 1 31 VLAN ID [P]

1 0 0 Control Register

1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2

50

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Page

0

LH: Latch High until clear SC: Self Clearing

Port 1 PHY Register

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RTL8305SC Datasheet Name

PHY

Register Register Description 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 16~17 Internal Use Register 18~19 Internal Use Register 22 Port 1 Control Register 0 23 Global Option Register 0 24 Port 1 Control Register 1 & VLAN ID[B] Membership 25 Port 1 Control Register 2 & VLAN ID[B]

0 26 Reserved 1 26 VLAN ID [G] Membership 0 27 Reserved 1 27 VLAN ID [G] 0 28 Reserved 1 28 VLAN ID [L] Membership 0 29 Reserved 1 29 VLAN ID [L]

2 0 0 Control Register

1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 16~17 Internal Use Register 18~19 Internal Use Register 22 Port 2 Control Register 0 24 Port 2 Control Register 1 & VLAN ID[C] Membership 25 Port 2 Control Register 2 & VLAN ID [C]

0 26 Reserved 1 26 VLAN ID [H] Membership 0 27 Reserved 1 27 VLAN ID [H] 0 28 Reserved 1 28 VLAN ID [M] Membership 0 29 Reserved 1 29 VLAN ID [M]

3 0 0 Control Register

1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register

51

Track ID: JATR-1076-21 Rev. 1.2

Page

Port 2 PHY Register

Port 3 PHY Register

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet Name

PHY

Register Register Description 16~18 Switch MAC Address 19~21 Internal Use Register 22 Port 3 Control Register 0 24 Port 3 Control Register 1 & VLAN ID[D] Membership 25 Port 3 Control Register 2 & VLAN ID [D]

0 26 Reserved 1 26 VLAN ID [I] Membership 0 27 Reserved 1 27 VLAN ID [I] 0 28 Reserved 1 28 VLAN ID [N] Membership 0 29 Reserved 1 29 VLAN ID [N]

4 0 0 Control Register

1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 16 Indirect Access Control 17~20 Indirect Access Data 21 Internal Use Register 22 Port 4 Control Register 0 24 Port 4 Control Register 1 & VLAN ID[E] Membership 25 Port 4 Control Register 2 & VLAN ID [E]

0 26 Reserved 1 26 VLAN ID [J] Membership 0 27 Reserved 1 27 VLAN ID [J] 0 28 Reserved 1 28 VLAN ID [O] Membership 0 29 Reserved 1 29 VLAN ID [O]

5 0 0 Control Register

1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register

Page

Port 4 PHY Register

PHY Register for Port 4 MAC

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 52 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.1. PHY 0 Registers 7.1.1. PHY 0 Register 0 for Port 0: Control

Table 60. PHY 0 Register 0: Control

Reg.bit Name 0.15 Reset

0.14 Loopback (Digital loopback)

Description

1: PHY reset. This bit is self-clearing

1: Enable loopback. This will loopback TXD to RXD and ignore all activity on the cable media 0: Normal operation

This function is usable only when this PHY is operated in 10Base-T full duplex or 100Base-TX full duplex.

RW 1: 100Mbps

0: 10Mbps

When NWay is enabled, this bit reflects the result of auto-negotiation (Read only).

When NWay is disabled, this bit can be set through SMI. (Read/Write).

When 100FX mode is enabled, this bit=1 (Read only).

RW 1: Enable auto-negotiation process

0: Disable auto-negotiation process

This bit can be set through SMI (Read/Write).

When 100FX mode is enabled, this bit=0 (Read only).

100FX must be in Force Mode. In order to avoid errors, the RTL8305SC will ignore the action of this bit when writing Reg0.12 as 1 in 100FX mode.

RW 1: Power down. All functions will be disabled except SMI

function

0: Normal operation

RW 1: Electrically isolates the PHY from MII. PHY is still able

to respond to MDC/MDIO 0: Normal operation

RW/SC 1: Restart Auto-Negotiation process

0: Normal operation

RW 1: Full duplex operation

0: Half duplex operation

When NWay is enabled (Reg0.12=1), this bit reflects the result of auto-negotiation (Read only).

When NWay is disabled (Reg0.12=0, force mode of UTP or 100FX), this bit can be set through SMI (Read/Write).

100FX must be in Force Mode. In order to avoid errors, the RTL8305SC will ignore the action to this bit when writing Reg0.12 as 1 in 100FX mode. Mode RW/SC RW

Default 0 0

0.13 Speed Select From pin

0.12

Auto Negotiation Enable

From pin

0.11 Power Down 0

0.10 Isolate 0

0.9 0.8 Restart Auto

Negotiation Duplex Mode

0 From pin

0.[7:0] Reserved 0000 0000

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 53 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.1.2. PHY 0 Register 1 for Port 0: Status

Table 61. PHY 0 Register 1: Status

Reg.bit Name

1.15 100Base_T4 1.14 100Base_TX_FD 1.13 1.12 1.11

100Base_TX_HD 10Base_T_FD 10Base_T_HD

Mode RO RO RO RO RO RO RO

Description

0: No 100Base-T4 capability

1: 100Base-TX full duplex capable 0: Not 100Base-TX full duplex capable 1: 100Base-TX half duplex capable 0: Not 100Base-TX half duplex capable 1: 10Base-TX full duplex capable 0: Not 10Base-TX full duplex capable 1: 10Base-TX half duplex capable 0: Not 10Base-TX half duplex capable

The RTL8305SC will accept management frames with preamble suppressed.

(The RTL8305SC accepts management frames without preamble. Minimum preamble of 32 bits is required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as defined in IEEE 802.3u).

1: Auto-negotiation process completed. MII Reg.4 and 5 are valid if this bit is set

0: Auto-negotiation process not completed 1: Remote fault condition detected 0: No remote fault

When in 100FX mode, this bit means in-band signal Far-End-Fault is detected

1: NWay auto-negotiation capable (permanently=1)

Default 0 1 1 1 1 0000 1

1.[10:7] Reserved 1.6 MF Preamble

Suppression

1.5

Auto-negotiate Complete Remote Fault

RO 0

1.4 RO/LH 0

1.3

Auto-Negotiation Ability

1.2 Link Status

RO 1 0

1.1 Jabber Detect 1.0

Extended Capability

RO/LL 1: Link is established. If the link fails, this bit will be 0 until

after reading this bit again 0: Link has failed

RO/LH 0: No Jabber detected

The RTL8305SC does not support this function.

RO 1: Extended register capable (permanently=1)

0 1

7.1.3. PHY 0 Register 2 for Port 0: PHY Identifier 1

Table 62. PHY 0 Register 2: PHY Identifier 1

Reg.bit Name Mode Description

2.[15:0] OUI RO Composed of the 3rd to 18th bits of the Organizationally Unique

Identifier (OUI), respectively

Default 0x001C

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RTL8305SC Datasheet 7.1.4. PHY 0 Register 3 for Port 0: PHY Identifier 2

Table 63. PHY 0 Register 3: PHY Identifier 2

Reg.bit 3.[15:10] 3.[9:4] 3.[3:0]

Name OUI

Model Number Revision Number

Mode RO RO RO

Description

Assigned to the 19th through 24th bits of the OUI

Manufacturer’s model number (05: Indicates RTL8305 Manufacturer’s revision number (02: Indicates SC

=

Default 110010 000101 0010

7.1.5. PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement

Note: Each time the link ability of the RTL8305SC is reconfigured, the auto-negotiation process should be executed to allow the configuration to take effect.

Table 64. PHY 0 Register 4: Auto-Negotiation Advertisement

Reg.bit 4.15

Name Next Page

Mode Description

RO 1: Next Page enabled

0: Next Page disabled (Permanently=0)

=0 RO Permanently

RW 1: Advertises that the RTL8305SC has detected a remote fault

0: No remote fault detected RO RW 1: Advertises that the RTL8305SC possesses 802.3x flow

control capability

0: No flow control capability

RO Technology not supported. (Permanently=0) RW 1: 100Base-TX full duplex capable

0: Not 100Base-TX full duplex capable RW 1: 100Base-TX half duplex capable

0: Not 100Base-TX half duplex capable RW 1: 10Base-TX full duplex capable

0: Not 10Base-TX full duplex capable RW 1: 10Base-TX half duplex capable

0: Not 10Base-TX half duplex capable RW [00001]IEEE 802.3

Default

0 0 0 00 From pin

4.14 Acknowledge 4.13 Remote Fault 4.[12:11] Reserved 4.10 Pause 4.9 4.8 4.7 4.6 4.5

100Base-T4 100Base-TX-FD 100Base-TX 10Base-T-FD 10Base-T

0 From pin From pin From pin

1 00001 4.[4:0] Selector Field

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 55 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.1.6. PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner

Ability

Table 65. PHY 0 Register 5: Auto-Negotiation Link Partner Ability

Reg.bit 5.15

Name Next Page

Mode Description

RO 1: Link partner desires Next Page transfer =

0: Link partner does not desire Next Page transfer RO 1: Link Partner acknowledges reception of Fast Link Pulse (FLP)

words

0: Not acknowledged by Link Partner RO 1: Remote Fault indicated by Link Partner

0: No remote fault indicated by Link Partner RO

RO 1: Flow control supported by Link Partner

0: Flow control not supported by Link Partner RO 1: 100Base-T4 supported by Link Partner

0: 100Base-T4 not supported by Link Partner

RO 1: 100Base-TX full duplex supported by Link Partner

0: 100Base-TX full duplex not supported by Link Partner

For 100FX mode, this bit will be set if Reg.0.8=1 or Full=1 after link is established

When auto negotiation is disabled, this bit will be set if Reg0.13=1 and Reg0.8=1 after link is established. RO 1: 100Base-TX half duplex supported by Link Partner

0: 100Base-TX half duplex not supported by Link Partner

For 100FX mode, this bit is set when Reg.0.8=1 or Full=1 after link established.

When auto negotiation is disabled, this bit will be set if Reg0.13=1 and Reg0.8=0 after link is established. RO 1: 10Base-TX full duplex supported by Link Partner

0: 10Base-TX full duplex not supported by Link Partner When auto negotiation is disabled, this bit will be set if Reg0.13=0 and Reg0.8=1 after link is established. RO 1: 10Base-TX half duplex supported by Link Partner

0: 10Base-TX half duplex not supported by Link Partner When auto negotiation is disabled, this bit will be set if Reg0.13=0 and Reg0.8=0 after link is established. RO [00001]IEEE 802.3

Default

0 0

5.14 Acknowledge 5.13 Remote Fault 0 00 0 0 0

5.[12:11] Reserved 5.10 Pause 5.9 5.8

100Base-T4 100Base-TX-FD

5.7 100Base-TX 0

5.6 10Base-T-FD 0

5.5 10Base-T 0

5.[4:0] Selector Field 00001

7.1.7. PHY 0 Register 16: Global Control 0

Table 66. PHY 0 Register 16: Global Control 0

Reg.bit Name

16.15 Page selection 16.14 Reserved Mode Description

RW 1: Select the registers in page 1

0: Select the registers in page 0

56

Default 0 0

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5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet Reg.bit Name

16.13 Lookup table

accessible enable

16.12 Software Reset

Mode Description

RW 1: Lookup table is accessible via indirect access registers

0: Lookup table is not accessible RW 1: Soft reset. This bit is self-clearing

SC If this bit is set to 1, the RTL8305SC will reset all internal

registers except PHY registers, and will not load configurations from EEPROM or strapping pins. Software reset is designed to provide a convenient way for users to change the configuration via SMI. After changing register values in the RTL8305SC (except PHY registers) via SMI, the external device must execute a soft reset (by setting this bit to 1) in order to update the configuration.

16.11 Reserved

16.10 Disable 802.1Q tag RW 1: Disable 802.1Q tagged-VID Aware function. The

aware VLAN RTL8305SC will not check the tagged VID on received frames

to perform tagged-VID VLAN mapping. Under this

configuration, the RTL8305SC only uses the per-port VLAN index register to perform Port-Based VLAN mapping

0: Enable the Member Set Filtering function of the VLAN Ingress Rules. The RTL8305SC checks the tagged VID on

received frames with the VIDA[11:0]~VIDH[11:0] to index to a member set, then performs VLAN mapping. The RTL8305SC uses tagged-VID VLAN mapping for tagged frames but still uses Port-Based VLAN mapping for priority-tagged and untagged frames

16.9 RW 1: The switch will not drop the received frame if the ingress port Disable VLAN

member set ingress of this packet is not included in the matched VLAN member set. filtering It will still forward the packet to the VLAN members specified

in the matched member set. This setting both works on port-based and tag-based VLAN configurations

0: The switch will drop the received frame if the ingress port of this packet is not included in the matched VLAN member set

16.8 RW 1: The switch accepts all frames it receives whether tagged or Disable VLAN tag

admit control untagged

0: The switch will only accept tagged frames and will drop untagged frames

16.7 RO 1: EEPROM does not exist (pin EnEEPROM=0 or pin EEPROM

existence EnEEPROM=1 but EEPROM does not exist)

0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists)

16.6 Internal Use RW 16.5 Internal Use RW 16.4 Internal Use RW 16.3 Internal Use RW 16.2 RW 1: Enable loop detection function Enable loop

detection function 0: Disable loop detection function

16.1 Reserved RW 16.0 Internal Use RW

Default

0 0

0 1

1

1

1

1 1 1 1 0 1 0

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

57 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.1.8. PHY 0 Register 17: Global Control 1

Table 67. PHY 0 Register 17: Global Control 1

Reg.bit Name 17.15 Internal Use 17.14 Internal Use 17.[13:8] Internal Use 17.7 Internal Use 17.6 Internal Use 17.[5:0] Internal Use

Mode Description RW RW RW RW RW RW

=

Default

0 0 11 1111 0 0 11 1111

7.1.9. PHY 0 Register 18: Global Control 2

Table 68. PHY 0 Register 18: Global Control 2

Reg.bit Name

18.15 Reserved 18.14 Maximum Frame

Length 18.13

Enable broadcast drop

Mode Description RW RW 1: 1536Bytes

0: 1552Bytes RW

1: Use Broadcast Input drop mechanism 0: Use Broadcast Output drop mechanism

Default Default1 Pin Max1536 strap option

=Default=1 Pin BCInDrop strap option Default=1 Pin EnForward strap option Default=1 Pin DisLeaky strap option Default=1 Pin DisARP strap option Default=1 Pin En48pass1 strap option Default=1 Pin DISVLAN strap option Default=1

18.12

Forward 802.1D reserved MAC addresses frame. Disable leaky VLAN

RW

18.11

18.10

Disable ARP VLAN

18.9 Enable 48 pass 1

18.8 Disable VLAN

18.7 Reserved 1: Forward reserved control frames, whose DID=01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F packets 0: Filter reserved control packets, whose DID=01-80-C2-00-00-02 and 01-80-C2-00-00-04 to 01-80-C2-00-00-0F RW 1: Disable forwarding of unicast frames to other VLANs

0: Enable forwarding of unicast frames to other VLANs Broadcast and multicast frames adhere to the VLAN configuration

RW 1: Disable broadcasting of ARP broadcast packets to all

VLANs

0: Enable broadcasting of ARP broadcast packets to all VLANs ARP broadcast frame DID is all F

RW 1: 48 pass 1. Continuously collides 48 input packets then

passes 1 packet to retain system resources and avoid partition in the repeater when the packet buffer is full

0: Continuously collides to avoid packet loss when the packet buffer is full

RW 1: Disable VLAN

0: Enable VLAN. The default VLAN membership

configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual VLANs. This default membership configuration may be modified by setting up internal registers via the SMI interface or EEPROM RW

58

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RTL8305SC Datasheet Reg.bit Name 18.6 Enable defer

Mode Description

RW 1: Enable carrier sense deferring for half duplex back pressure

0: Disable carrier sense deferring for half duplex back pressure RW

1: On for 43ms, then Off for 43ms 0: On for 120ms, then Off for 120ms

Default Pin EnDefer strap option Default=1 Pin LED_BLNK_TIME strap option Default=1

=Pin

QWeight[1:0] strap option Default=11

18.5 LED blink time

18.[4:3] Queue weight

18.2

Disable broadcast

storm control

RW The frame service ratio between the high priority queue and

low priority queue is: 11=16:1

10=Always high priority queue first 01=8:1 00=4:1

RW 1: Disable Broadcast Storm Control

0: Enable Broadcast Storm Control RW

1: Enable power-on LED blinking for diagnosis 0: Disable power-on LED blinking for diagnosis

18.1

Enable power-on blinking

18.0 Reserved

Pin DisBrdCtrl strap option Default=1 Pin

En_Rst_Blnk strap option Default=1

1

7.1.10. PHY 0 Register 19: Global Control 3

Table 69. PHY 0 Register 19: Global Control 3

Reg.bit Name Mode Description

19.[15:14Reserved ]

RW 11=Mode 3: Speed, Link+Act, Duplex+Col, Link/Act/Speed 19.[13:12LED Mode[1:0]

] 10=Mode 2: Speed, Act, Duplex/Col, Bi-color Link/Activity

01=Mode 1: Speed, RxAct, TxAct, Link 00=Mode 0: Reserved

19.11 Internal Use RW

19.10 Disable dual MII RW 1: Disable dual MII interface of port 4. Only provides MII

interface of interface for the MAC circuit of port 4 Port 4 0: Enable dual MII interface of port 4. Provides MII interface

for the MAC circuit of port 4, and also provides MII interface for the PHY circuit of port 4

19.[9:0] Reserved

Default

11 Pin

LEDMode[1:0] strap option Default=11 Default1 Pin

DISDUALMII strap option Default=1 11 1111 1111

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RTL8305SC Datasheet 7.1.11. PHY 0 Register 22: Port 0 Control Register 0

Table 70. PHY 0 Register 22: Port 0 Control Register 0

Reg.bit Name

22.15 Reserved 22.14 Internal Use 22.13 Port 0 Local

loopback 22.12 Internal Use 22.11 Port 0 Non PVID

packets Discard

Mode Description Default 1 RW 0 RW 1: Perform ‘local loopback’, i.e. loop MAC’s RX back to TX. 0

0: Normal operation RW 0 RW 1: If the received packets are tagged, the switch will discard 0

packets whose VID does not match the ingress port default VID, which is indexed by port 0’s ‘Port based VLAN index’ 0: No packets will be discarded

RW 1: Disable 802.1p priority classification for ingress packets on Pin

port 0 DisTagPri

strap option 0: Enable 802.1p priority classification

Default=1

RW 1: Disable Diffserv priority classification for ingress packets on Pin DisDSPri

port 0 strap option 0: Enable Diffserv priority classification Default=1 RW 1: Disable port-based priority QoS function on port 0 Pin

DisPortPri[0] 0: Enable port-based priority QoS function on port 0. Ingress

strap option packet on port 0 will be classified as high priority

Default=1

0 RW 1 RW 1 RW 1 RW 1

11 RW 11=Do not insert or remove VLAN tags to/from packets that are

output on this port

10=The switch will add VLAN tags to packets, if they are not tagged when these packets are output on this port. The switch will not add tags to packets already tagged. The inserted tag is the ingress port’s ‘Default tag’, which is indexed by port 0’s ‘Port based VLAN index’

01=The switch will remove VLAN tags from packets if they are tagged when these packets are output on port 0. The switch will not modify packets received without tags

00=The switch will remove VLAN tags from packets then add new tags to them. The inserted tag is the ingress port’s ‘Default tag’, which is indexed by port 0’s ‘Port based VLAN index’. This is a replacement processing for tagged packets and an insertion for untagged packets

22.10

Port 0 802.1p priority Disable

22.9

Port 0 Diffserv priority Disable Port 0 port-based priority Disable

22.8

22.7 Reserved 22.6 Internal Use 22.[5:4] Internal Use 22.3 Internal Use 22.2 Internal Use 22.[1:0] Port 0 VLAN tag

insert and remove

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RTL8305SC Datasheet 7.1.12. PHY 0 Register 24: Port 0 Control Register 1 & VLAN ID [A]

Membership

Table 71. PHY 0 Register 24: Port 0 Control Register 1 & VLAN ID [A] Membership

Reg.bit Name Mode Description

24.[15:12Port 0 VLAN index RW In a port-based VLAN configuration, this register indexes to

] [3:0] port 0’s ‘Port VLAN Membership’, which can be defined in

one of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [P] Membership’.

Port 0 can only communicate with members within this VLAN. This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0000, which indexes to the VLAN entry [A] that is composed of VLAN ID[A]

Membership Bit [4:0] in PHY0 Reg.24.[4:0], and VLAN ID [A] in PHY0 Reg.25.[11:0].

24.11 Internal Use RW 24.10 Internal Use RW 24.9 Internal Use RW 24.8 Internal Use RO 24.7 Internal Use RW

Internal Use 24.6 RW 24.5 Reserved 24.[4:0] VLAN ID [A] RW This 5-bit field specifies which ports are the members of

Membership Bit VLAN A. If a destination address look up fails, the packet [4:0] associated with this VLAN will be broadcast to the ports

specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4.E.g.:

10001 means port 4 and 0 are the members of VLAN A 10010 means port 4 and 1 are the members of VLAN A 11111 means all 5 ports are the members of VLAN A

Default 0000

1 1 1 0 1 1 0 1 0001

7.1.13. PHY 0 Register 25: Port 0 Control Register 2 & VLAN ID [A]

Table 72. PHY 0 Register 25: Port 0 Register Control 2 & VLAN ID [A]

Reg.bit Name 25.15 Internal Use 25.14 Internal Use 25.13 Internal Use 25.12 Internal Use 25.[11:0] VLAN ID [A]

Mode Description RW RW RW RW

RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A

Default 1 1 1 1 0x000

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RTL8305SC Datasheet 7.1.14. PHY 0 Register 26: Reserved or VLAN ID [F] Membership

7.1.14.1 PHY 0 Register 26: Reserved Register (Page=0)

Table 73. PHY 0 Register 26: Reserved Register

Reg.bit Name 26.[15:0] Reserved Mode Description

Default

0x5105

7.1.14.2 PHY 0 Register 26: VLAN ID [F] Membership (Page=1)

Table 74. PHY 0 Register 26: VLAN ID [F] Membership

Reg.bit Name 26.[15:5] Reserved 26.[4:0] VLAN ID [F]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN

F. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN F 10010 means port 4 and 1 are the members of VLAN F 11111 means all 5 ports are the members of VLAN F

Default 1111 1111 111 1 0001

7.1.15. PHY 0 Register 27: Reserved or VLAN ID [F]

7.1.15.1 PHY 0 Register 27: Reserved Register (Page=0)

Table 75. PHY 0 Register 27: Reserved Register

Reg.bit Name 27.[15:0] Reserved Mode Description

Default 0x0000

7.1.15.2 PHY 0 Register 27: VLAN ID [F] (Page=1)

Table 76. PHY 0 Register 27: VLAN ID [F]

Reg.bit Name Mode Description

27.[15:12Reserved ]

27.[11:0] VLAN ID [F] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN F

Default

1111 0000 0000 0101

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RTL8305SC Datasheet 7.1.16. PHY 0 Register 28: Reserved or VLAN ID [K] Membership

7.1.16.1 PHY 0 Reg.28: Reserved Register (Page=0)

Table 77. PHY 0 Register 28: Reserved Register

Reg.bit Name 28.[15:0] Reserved Mode Description

Default 0x0020

7.1.16.2 PHY 0 Register 28: VLAN ID [K] Membership (Page=1)

Table 78. PHY 0 Register 28: VLAN ID [K] Membership

Reg.bit Name 28.[15:5] Reserved 28.[4:0]

VLAN ID [K] Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of

VLAN K. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN K 10010 means port 4 and 1 are the members of VLAN K 11111 means all 5 ports are the members of VLAN K

Default 1111 1111 111 1 0001

7.1.17. PHY 0 Register 29: Reserved or VLAN ID [K]

7.1.17.1 PHY 0 Register 29: Reserved Register (Page=0)

Table 79. PHY 0 Register 29: Reserved Register

Reg.bit Name 29.[15:0] Reserved Mode Description

Default

7.1.17.2 PHY 0 Register 29: VLAN ID [K] (Page=1)

Table 80. PHY 0 Register 29: VLAN ID [K]

Reg.bit Name Mode Description

29.[15:12Reserved ]

29.[11:0] VLAN ID [K] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN K

Default

1111 0000 0000 1010

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RTL8305SC Datasheet 7.1.18. PHY 0 Register 30: Reserved or VLAN ID [P] Membership

7.1.18.1 PHY 0 Register 30: Reserved Register (Page=0)

Table 81. PHY 0 Register 30: Reserved Register

Reg.bit Name 30.[15:0] Reserved Mode Description

Default

7.1.18.2 PHY0 Register 30: VLAN ID [P] Membership (Page=1)

Table 82. PHY 0 Register 30: VLAN ID [P] Membership

Reg.bit Name 30.[15:5] Reserved 30.[4:0] VLAN ID [P]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of

VLAN P. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN P 10010 means port 4 and 1 are the members of VLAN P 11111 means all 5 ports are the members of VLAN P

Default 1111 1111 111 1 0001

7.1.19. PHY 0 Register 31: Reserved or VLAN ID [P]

7.1.19.1 PHY 0 Register 31: Reserved Register (Page=0)

Table 83. PHY 0 Register 31: Reserved Register

Reg.bit Name 31.[15:0] Reserved Mode Description

Default

7.1.19.2 PHY 0 Register 31: VLAN ID [P] (Page=1)

Table 84. PHY 0 Register 31: VLAN ID [P]

Reg.bit Name Mode Description

31.[15:12Reserved ]

31.[11:0] VLAN ID [P] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN P

Default

1111 0000 0000 1111

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 64 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.2. PHY 1 Registers 7.2.1. PHY 1 Register 0 for Port 1: Control

This register has the same definition as PHY 0 Register 0 for Port 0: Control, page 53.

7.2.2. PHY 1 Register 1 for Port 1: Status

This register has the same definition as PHY 0 Register 1 for Port 0: Status, page 54.

7.2.3. PHY 1 Register 2 for Port 1: PHY Identifier 1

This register has the same definition as PHY 0 Register 2 for Port 0: PHY Identifier 1, page 54.

7.2.4. PHY 1 Register 3 for Port 1: PHY Identifier 2

This register has the same definition as PHY 0 Register 3 for Port 0: PHY Identifier 2, page 55.

7.2.5. PHY 1 Register 4 for Port 1: Auto-Negotiation Advertisement

This register has the same definition as PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement, page 55.

7.2.6. PHY 1 Register 5 for Port 1: Auto-Negotiation Link Partner

Ability

This register has the same definition as PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability, page 56.

7.2.7. PHY 1 Register 16~17: Internal Use Register

Table 85. PHY 1 Register 16~17: Internal Use Register

Reg.bit Name

16 Internal Use 17 Internal Use

Mode Description

RW RW

Default

0xFFFF 0xFFFF

7.2.8. PHY 1 Register 18~19: Internal Use Register

Table 86. PHY 1 Register 18~19: Internal Use Register

Reg.bit Name

18 Internal Use 19 Internal Use

Mode Description

RW RW

65

Default

0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev. 1.2

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet 7.2.9. PHY 1 Register 22: Port 1 Control Register 0

This register has the same definition as PHY 0 Register 22: Port 0 Control Register 0page 60. Note: Reg 22.8 is pin DisPortPri[1] strap option for port 1. Default value for 22.8 is 1.

7.2.10. PHY 1 Register 23: Global Option Register 0

Table 87. PHY 1 Register 23: Global Option Register 0

Reg.bit Name

23.15 Reserved 23.14 Internal Use 23.[13:8] Reserved 23.7 Internal Use 23.[6:5] Reserved 23.4 Internal Use 23.[3:0] Reserved Mode Description RW RW RW

Default

1 0 00 1111 0 10 1 1111

7.2.11. PHY 1 Register 24: Port 1 Control Register 1 & VLAN ID [B]

Membership

Table 88. PHY 1 Register 24: Port 1 Control Register 1 & VLAN ID [B] Membership

Reg.bit Name Mode Description

24.[15:12Port 1 VLAN index RW In a port-based VLAN configuration, this register indexes to

] [3:0] port 1’s ‘Port VLAN Membership’, which can be defined in one

of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [P] Membership”. Port 1can only communicate with members within this VLAN.

This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0001, which indexes to the VLAN entry [B] that is composed of VLAN ID [B]

Membership Bit [4:0] in PHY1 Reg.24.[4:0] and VLAN ID [B] in PHY1 Reg.25.[11:0].

24.11 Internal Use RW 24.10 Internal Use RW 24.9 Internal Use RW 24.8 Internal Use RO 24.7 Internal Use RW 24.6 Internal Use RW 24.5 Reserved

Default

0001

1 1 1 0 1 1 0

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 66 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Reg.bit Name

24.[4:0] VLAN ID [B]

Membership Bit [4:0]

Mode Description

RW This 5-bit field specifies which ports are the members of VLAN

B. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN B 10010 means port 4 and 1 are the members of VLAN B 11111 means all 5 ports are members of VLAN B

Default 1 0010

7.2.12. PHY 1 Register 25: Port 1 Control Register 2 & VLAN ID [B]

Table 89. PHY 1 Register 25: Port 1 Control Register 2 & VLAN Entry [B]

Reg.bit Name 25.15 Internal Use 25.14 Internal Use 25.13 Internal Use 25.12 Internal Use 25.[11:0] VLAN ID [B]

Mode Description RW RW RW RW

RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN B

Default 1 1 1 1 0000 0000 0001

7.2.13. PHY 1 Register 26: Reserved or VLAN ID [G] Membership

7.2.13.1 PHY 1 Register 26: Reserved Register (Page=0)

Table 90. PHY 1 Register 26: Reserved Register

Reg.bit Name 26.[15:0] Reserved Mode Description

Default 0x031F

7.2.13.2 PHY 1 Register 26: VLAN ID [G] Membership (Page=1)

Table 91. PHY 1 Register 26: VLAN ID [G] Membership

Reg.bit Name 26.[15:5] Reserved 26.[4:0] VLAN ID [G]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN G.

If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for Port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN G 10010 means port 4 and 1 are the members of VLAN G 11111 means all 5 ports are members of VLAN G

Default 1111 1111 111 1 0010

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

67 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.2.14. PHY 1 Register 27: Reserved or VLAN ID [G]

7.2.14.1 PHY 1 Register 27: Reserved Register (Page=0)

Table 92. PHY 1 Register 27: Reserved Register

Reg.bit Name 27.[15:0] Reserved Mode Description

Default 0x1F10

7.2.14.2 PHY 1 Register 27: VLAN ID [G] (Page=1)

Table 93. PHY 1 Register 27: VLAN ID [G]

Reg.bit Name Mode Description

27.[15:12Reserved ]

27.[11:0] VLAN ID [G] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN G

Default

1111 0000 0000 0110

7.2.15. PHY 1 Register 28: Reserved or VLAN ID [L] Membership

7.2.15.1 PHY 1 Register 28: Reserved Register (Page=0)

Table 94. PHY 1 Register 28: Reserved Register

Reg.bit Name 28.[15:0] Reserved Mode Description

Default 0x0012

7.2.15.2 PHY 1 Register 28: VLAN ID [L] Membership (Page=1)

Table 95. PHY 1 Register 28: VLAN ID [L] Membership

Reg.bit Name

28.[15:5] Reserved 28.[4:0]

VLAN ID [L] Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of

VLAN L. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN L 10010 means port 4 and 1 are the members of VLAN L 11111 means all 5 ports are members of VLAN L

Default 1111 1111 111 1 0010

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 68 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.2.16. PHY 1 Register 29: Reserved or VLAN ID [L]

7.2.16.1 PHY 1 Register 29: Reserved (Page=0)

Table 96. PHY 1 Register 29: Reserved Register

Reg.bit Name 29.[15:0] Reserved Mode Description

Default 0x02C5

7.2.16.2 PHY 1 Register 29: VLAN ID [L] (Page=1)

Table 97. PHY 1 Register 29: VLAN ID [L]

Reg.bit Name Mode Description

29.[15:12Reserved ]

29.[11:0] VLAN ID [L] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN L

Default

1111 0000 0000 1011

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 69 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.3. PHY 2 Registers 7.3.1. PHY 2 Register 0 for Port 2: Control

This register has the same definition as PHY 0 Register 0 for Port 0: Control, page 53.

7.3.2. PHY 2 Register 1 for Port 2: Status

This register has the same definition as PHY 0 Register 1 for Port 0: Status, page 54.

7.3.3. PHY 2 Register 2 for Port 2: PHY Identifier 1

This register has the same definition as PHY 0 Register 2 for Port 0: PHY Identifier 1, page 54.

7.3.4. PHY 2 Register 3 for Port 2: PHY Identifier 2

This register has the same definition as PHY 0 Register 3 for Port 0: PHY Identifier 2, page 55.

7.3.5. PHY 2 Register 4 for Port 2: Auto-Negotiation Advertisement

This register has the same definition as PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement, page 55.

7.3.6. PHY 2 Register 5 for Port 2: Auto-Negotiation Link Partner

Ability

This register has the same definition as PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability, page 56.

7.3.7. PHY 2 Register 16~17: Internal Use Register

Table 98. PHY 2 Register 16~17: Internal Use Register

Reg.bit Name

16 Internal Use 17 Internal Use

Mode Description

RW RW

Default

0xFFFF 0xFFFF

7.3.8. PHY 2 Register 18~19: Internal Use Register

Table 99. PHY 2 Register 18~19: Internal Use Register

Reg.bit Name

18 Internal Use 19 Internal Use

Mode Description

RW RW

70

Default

0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev. 1.2

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

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RTL8305SC Datasheet 7.3.9. PHY 2 Register 22: Port 2 Control Register 0

This register has the same definition as PHY 0 Register 22: Port 0 Control Register 0, on page 60. Note: Reg 22.8 is pin DisPortPri[2] strap option for port 2. Default value for 22.8 is 1.

7.3.10. PHY 2 Register 23: Global Option 1 Register

Table 100. PHY 2 Register 23: Global Option Register 1

Reg.bit Name Mode Description 23.[15:12Reserved

]

23.11 Internal Use RW 23.10 Internal Use RW 23.9 Internal Use RW 23.[8:0] Reserved

Default

0000 0 0 0 0 0010 0000

7.3.11. PHY 2 Register 24: Port 2 Control Register 2 & VLAN ID [C]

Membership

Table 101. PHY 2 Register 24: Port 2 Control Register 2 & VLAN ID [C] Membership

Reg.bit Name Mode Description

24.[15:12Port 2 VLAN index RW In a port-based VLAN configuration, this register indexes to

] [3:0] port 2’s ‘Port VLAN Membership’, which can be defined in one

of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [P] Membership’. Port 2 can only communicate with members within this VLAN.

This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0010, which indexes to the VLAN entry [C] that is composed of VLAN ID [C]

Membership Bit [4:0] in PHY2 Reg.24.[4:0], and VLAN ID [C] in PHY2 Reg.25.[11:0].

24.11 Internal Use RW 24.10 Internal Use RW 24.9 Internal Use RW 24.8 Internal Use RO

24.7 Internal Use RW Internal Use 24.6 RW

24.5 Reserved

Default

0010

1 1 1 0 1 1 0

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RTL8305SC Datasheet Reg.bit Name

24.[8:0] VLAN ID [C]

Membership Bit [4:0]

Mode Description

RW This 5-bit field specifies which ports are the members of VLAN

C. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN C 10010 means port 4 and 1 are the members of VLAN C 11111 means all 5 ports are the members of VLAN C

Default 1 0100

7.3.12. PHY 2 Register 25: Port 2 Control Register 3 & VLAN ID [C]

Table 102. PHY 2 Register 25: Port 2 Control Register 3 & VLAN ID [C]

Reg.bit Name 25.15 Internal Use 25.14 Internal Use 25.13 Internal Use 25.12 Internal Use 25.[11:0] VLAN ID [C]

Mode Description RW RW RW RW

RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C

Default 1 1 1 1 0000 0000 0010

7.3.13. PHY 2 Register 26: Reserved or VLAN ID [H] Membership

7.3.13.1 PHY 2 Register 26: Reserved Register (Page=0)

Table 103. PHY 2 Register 26: Reserved Register

Reg.bit Name 26.[15:0] Reserved Mode Description

Default 0x0052

7.3.13.2 PHY 2 Register 26: VLAN ID [H] Membership (Page=1)

Table 104. PHY 2 Register 26: VLAN ID [H] Membership

Reg.bit Name 26.[15:5] Reserved 26.[4:0] VLAN ID [H]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN

H. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN H 10010 means port 4 and 1 are the members of VLAN H 11111 means all 5 ports are the members of VLAN H

Default 1111 1111 111 1 0100

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

72 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.3.14. PHY 2 Register 27: Reserved or VLAN ID [H]

7.3.14.1 PHY 2 Register 27: Reserved Register (Page=0)

Table 105. PHY 2 Register 27: Reserved Register

Reg.bit Name 27.[15:0] Reserved Mode Description

Default 0xA9CD

7.3.14.2 PHY 2 Register 27: VLAN ID [H] (Page=1)

Table 106. PHY 2 Register 27: VLAN ID [H]

Reg.bit Name Mode Description

27.[15:12Reserved ]

27.[11:0] VLAN ID [H] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN H

Default

1111 0000 0000 0111

7.3.15. PHY 2 Register 28: Reserved or VLAN ID [M] Membership

7.3.15.1 PHY 2 Register 28: Reserved Register (Page=0)

Table 107. PHY 2 Register 28: Reserved Register

Reg.bit Name 28.[15:0] Resreved Mode Description

Default 0xB029

7.3.15.2 PHY 2 Register 28: VLAN ID [M] Membership (Page=1)

Table 108. PHY 2 Register 28: VLAN ID [M] Membership

Reg.bit Name 28.[15:5] Reserved 28.[4:0] VLAN ID [M] Membership Bit [4:0]

Mode Description RW

Default 1111 1111 111 1 0100 This 5-bit field specifies which ports are the members of VLAN M. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN M 10010 means port 4 and 1 are the members of VLAN M 11111 means all 5 ports are the members of VLAN M

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 73 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.3.16. PHY 2 Register 29: Reserved or VLAN ID [M]

7.3.16.1 PHY 2 Register 29: Reserved Register (Page=0)

Table 109. PHY 2 Register 29: Reserved Register

Reg.bit Name 29.[15:0] Reserved Mode Description

Default 0xB01F

7.3.16.2 PHY 2 Register 29: VLAN ID [M] (Page=1)

Table 110. PHY 2 Register 29: VLAN ID [M]

Reg.bit Name Mode Description

29.[15:12Reserved ]

29.[11:0] VLAN ID [M] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN M.

Default

1111 0000 0000 1100

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RTL8305SC Datasheet 7.4. PHY 3 Registers 7.4.1. PHY 3 Register 0 for Port 3: Control

This register has the same definition as PHY 0 Register 0 for Port 0: Control, page 53.

7.4.2. PHY 3 Register 1 for Port 3: Status

This register has the same definition as PHY 0 Register 1 for Port 0: Status, page 54.

7.4.3. PHY 3 Register 2 for Port 3: PHY Identifier 1

This register has the same definition as PHY 0 Register 2 for Port 0: PHY Identifier 1, page 54.

7.4.4. PHY 3 Register 3 for Port 3: PHY Identifier 2

This register has the same definition as PHY 0 Register 3 for Port 0: PHY Identifier 2, page 55.

7.4.5. PHY 3 Register 4 for Port 3: Auto-Negotiation Advertisement

This register has the same definition as PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement, page 55.

7.4.6. PHY 3 Register 5 for Port 3: Auto-Negotiation Link Partner

Ability

This register has the same definition as PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability, page 56.

7.4.7. PHY 3 Register 16~18: Switch MAC Address

The Switch MAC address is used as the source address in MAC pause control frames.

Table 111. PHY 3 Register 16~18: Switch MAC Address

Reg.bit Name 16 Switch MAC

Address [47:32]

17 Switch MAC

Address [31:16]

18 Switch MAC

Address [15:0]

Mode Description

RW 16.[15:8] = Switch MAC Address Byte 4

16.[7:0] = Switch MAC Address Byte 5 RW 17.[15:8] = Switch MAC Address Byte 2

17.[7:0] = Switch MAC Address Byte 3 RW 18.[15:8] = Switch MAC Address Byte 0

18.[7:0] = Switch MAC Address Byte 1

Default 0x5452 0x834C 0xC005

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 75 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.4.8. PHY 3 Register 19~21: Internal Use Register

Table 112. PHY 3 Register 19~21: Internal Use Register

Reg.bit Name

19 Internal Use 20 Internal Use 21 Internal Use

Mode Description

RW RW RW

Default

0x0000 0x0000 0x0000

7.4.9. PHY 3 Register 22: Port 3 Control Register 0

This register has the same definition as PHY 0 Register 22: Port 0 Control Register 0, on page 60. Note: Reg 22.8 is pin DisPortPri[3] strap option for port 3. Default value for 22.8 is 1.

7.4.10. PHY 3 Register 24: Port 3 Control Register 1 & VLAN ID [D]

Membership

Table 113. PHY 3 Register 24: Port 3 Control Register 1 & VLAN ID [D] Membership

Reg.bit Name Mode Description

24.[15:12Port 3 VLAN index RW In a port-based VLAN configuration, this register indexes to

] [3:0] port 3’s ‘Port VLAN Membership’, which can be defined in one

of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [P] Membership’. Port 3 can only communicate with members within this VLAN.

This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0011, which indexes to the VLAN entry [D] that is composed of VLAN ID [D]

Membership Bit [4:0] in PHY3 Reg.24.[4:0], and VLAN ID [D] in PHY3 Reg.25.[11:0].

24.11 Internal Use RW 24.10 Internal Use RW 24.9 Internal Use RW 24.8 Internal Use RO 24.7 Internal Use RW 24.6 Internal Use 24.5 Reserved RW

Default 0011

1 1 1 0 From pin Default=1

1 0

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 76 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Reg.bit Name

24.[4:0] VLAN ID [D]

Membership Bit [4:0]

Mode Description

RW This 5-bit field specifies which ports are the members of VLAN

D. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN D 10010 means port 4 and 1 are the members of VLAN D 11111 means all 5 ports are the members of VLAN D

Default 1 1000

7.4.11. PHY 3 Register 25: Port 3 Control Register 2 & VLAN ID [D]

Table 114. PHY 3 Register 25: Port 3 Control Register 2 & VLAN ID [D]

Reg.bit Name 25.15 Internal Use 25.14 Internal Use 25.13 Internal Use 25.12 Internal Use 25[11:0] VLAN ID [D]

Mode Description RW RW RW RW

RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D

Default 1 1 1 1 0000 0000 0011

7.4.12. PHY 3 Register 26: Reserved or VLAN ID [I] Membership

7.4.12.1 PHY 3 Register 26: Reserved Register (Page=0)

Table 115. PHY 3 Register 26: Reserved Register

Reg.bit Name 26.[15:0] Reserved Mode Description

Default 0x9668

7.4.12.2 PHY 3 Register 26: VLAN ID [I] Membership (Page=1)

Table 116. PHY 3 Register 26: VLAN ID [I] Membership

Reg.bit Name 26.[15:5] Reserved 26.[4:0] VLAN ID [I]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN

I. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN I 10010 means port 4 and 1 are the members of VLAN I 11111 means all 5 ports are the members of VLAN I

Default 1111 1111 111 1 1000

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

77 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.4.13. PHY 3 Register 27: Reserved or VLAN ID [I]

7.4.13.1 PHY 3 Register 27: Reserved Register (Page=0)

Table 117. PHY 3 Register 27: Reserved Register

Reg.bit Name 27.[15:0] Reserved Mode Description

Default 0xA464

7.4.13.2 PHY 3 Register 27: VLAN ID [I] (Page=1)

Table 118. PHY 3 Register 27: VLAN ID [I]

Reg.bit Name Mode Description

27.[15:12Reserved ]

27.[11:0] VLAN ID [I] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN I

Default

1111 0000 0000 1000

7.4.14. PHY 3 Register 28: Reserved or VLAN ID [N] Membership

7.4.14.1 PHY 3 Register 28: Reserved Register (Page=0)

Table 119. PHY 3 Register 28: Reserved Register

Reg.bit Name 28.[15:0] Reserved Mode Description

Default 0x9458

7.4.14.2 PHY 3 Register 28: VLAN ID [N] Membership (Page=1)

Table 120. PHY 3 Register 28: VLAN ID [N] Membership

Reg.bit Name

28.[15:5] Reserved 28.[4:0]

VLAN ID [N] Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of

VLAN N. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN N 10010 means port 4 and 1 are the members of VLAN N 11111 means all 5 ports are the members of VLAN N

Default 1111 1111 111 1 1000

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 78 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.4.15. PHY 3 Register 29: Reserved or VLAN ID [N]

7.4.15.1 PHY 3 Register 29: Reserved Register (Page=0)

Table 121. PHY 3 Register 29: Reserved Register

Reg.bit Name 29.[15:0] Reserved Mode Description

Default 0x2154

7.4.15.2 PHY 3 Register 29: VLAN ID [N] (Page=1)

Table 122. PHY 3 Register 29: VLAN ID [N]

Reg.bit Name Mode Description

29.[15:12Reserved ]

29.[11:0] VLAN ID [N] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN N.

Default

1111 0000 0000 1101

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 79 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet 7.5. PHY 4 Registers 7.5.1. PHY 4 Register 0 for Port 4: Control

This register has the same definition as PHY 0 Register 0 for Port 0: Control, page 53.

7.5.2. PHY 4 Register 1 for Port 4: Status

This register has the same definition as PHY 0 Register 1 for Port 0: Status, page 54.

7.5.3. PHY 4 Register 2 for Port 4: PHY Identifier 1

This register has the same definition as PHY 0 Register 2 for Port 0: PHY Identifier 1, page 54.

7.5.4. PHY 4 Register 3 for Port 4: PHY Identifier 2

This register has the same definition as PHY 0 Register 3 for Port 0: PHY Identifier 2, page 55.

7.5.5. PHY 4 Register 4 for Port 4: Auto-Negotiation Advertisement

This register has the same definition as PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement, page 55.

7.5.6. PHY 4 Register 5 for Port 4: Auto-Negotiation Link Partner

Ability

This register has the same definition as PHY 0 Register 5 for Port 0: Auto-Negotiation Link Partner Ability, page 56.

7.5.7. PHY 4 Register 16: Indirect Access Control

PHY 4 register 16 is used for reading or writing data to the MAC address table.

Table 123. PHY 4 Register 16: Indirect Access Control

Reg.bit Name 16.[15:2] Reserved 16.1 16.0

Command execution Read or write operation

Mode Description RW RW

1: Trigger a command to read or write lookup table 0: Indicate this command is done 1: Read cycle 0: Write cycle

Default 0000 0000 0000 00 0

0

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RTL8305SC Datasheet 7.5.8. PHY 4 Register 17~20: Indirect Access Data

Table 124. PHY 4 Register 17~20: Indirect Access Data

Reg.bit Name 17 Indirect Data 0

[15:0]

Mode Description

RW Indirect Data 0 [6] = If this bit is 1, indicates this entry is static

and will never be aged out. If this bit is 0, indicates this entry is dynamically learned, aged, updated, and deleted.

Indirect Data [5:4] = 2-bit counter for internal aging. (10->11->01->00)

Indirect Data [3:0] = The source port of this Source MAC Address ID learned

Indirect Data 0 [15:7] = Reserved.

RW Indirect Data 1 [15:8] = Source MAC Address [7:0] (Byte 5)

Indirect Data 1 [7:0] = Source MAC Address [15:8] (Byte 4)

Indirect Data 1 [1:0] and Indirect Data 1 [15:8] of this register also determine the Entry Index [9:0] in the lookup table of this accessed data.

Indirect Data 1 [1:0] = Entry Index [9:8] Indirect Data 1 [15:8] = Entry Index [7:0]

In the write cycle: Entry Index [9:0] indirectly maps to an entry in the lookup table for writing. The written data must be the Source MAC Address [47:10] and Entry Index [9:0].

In the read cycle: Entry Index [9:0] indirectly maps to an entry in the lookup table for reading. The read back data will be shown in Indirect Data 0, 1, 2, and 3.

RW Indirect Data 2 [7:0] = Source MAC Address [31:24] (Byte 3)

Indirect Data 2 [15:8] = Source MAC Address [23:16] (Byte 2) RW Indirect Data 3 [7:0] = Source MAC Address [47:40] (Byte 1)

Indirect Data 3 [15:8] = Source MAC Address [39:32] (Byte 0)

Default 0x00

18

Indirect Data 1 [15:0]

0x00

19 20

Indirect Data 2 [15:0]

Indirect Data 3 [15:0]

0x00 0x00

7.5.9. PHY 4 Register 21: 802.1p Base Priority

Table 125. PHY 2 Register 20: 802.1p Base Priority

Reg.bit Name

21.[15.13802.1p base

] priority

Mode Description

RW Classifies priority for incoming IEEE 802.1Q packets, if

IEEE 802.1p priority classification is enabled. ‘User priority’ is compared against this value. >=: Classify as high priority <: Classify as low priority RW RW

81

Default 100

21.[12:7] Reserved 21.[6:4] Internal Use 21.3 Reserved 21.[2:0] Internal Use

0 0000 0

100 0 000

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RTL8305SC Datasheet 7.5.10. PHY 4 Register 22: Port 4 Control Register 0

This register has the same definition as PHY 0 Register 22: Port 0 Control Register 0, on page 60. Note: Reg 22.8 is not pin DisPortPri[4] strap option for port 4. Default value for 22.8 is 1.

7.5.11. PHY 4 Register 24: Port 4 Control Register 1 & VLAN ID [E]

Membership

Table 126. PHY 4 Register 24: Port 4 Control Register 1 & VLAN ID [E] Membership

Reg.bit Name Mode Description

24.[15:12Port 4 VLAN index RW In a port-based VLAN configuration, this register indexes to

] [3:0] port 4’s ‘Port VLAN Membership’, which can be defined in one

of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [P] Membership’. Port 4 can only communicate with members within this VLAN.

This register also indexes to a default Port VID (PVID) for each port. The PVID is used in tag insertion and filtering if the tagged VID is not the same as the PVID.

The default value of this register is 0100, which indexes to the VLAN entry [E] that is composed of VLAN ID [E] Membership Bit [4:0] in PHY4 Reg.24.[4:0], and VLAN ID [E] in PHY4 Reg.25.[11:0].

24.11 Internal Use RW 24.10 Internal Use RW 24.9 Internal Use RW 24.8 Internal Use RO 24.7 Internal Use RW 24.6 Internal Use RW 24.5 Reserved 24.[4:0] VLAN ID [E] RW This 5-bit field specifies which ports are the members of VLAN

Membership Bit E. If a destination address look up fails, the packet associated [4:0] with this VLAN will be broadcast to the ports specified in this

field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN E 10010 means port 4 and 1 are the members of VLAN E 11111 means all 5 ports are the members of VLAN E

Default 0100

1 1 1 0 1 1 0 1 1111

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RTL8305SC Datasheet 7.5.12. PHY 4 Register 25: Port 4 Control Register 2 & VLAN ID [E]

Table 127. PHY 4 Register 25: Port 4 Control Register 2 & VLAN ID [E]

Reg.bit Name 25.15 Internal Use 25.14 Internal Use 25.13 Internal Use 25.12 Internal Use 25.[11:0] VLAN ID [E]

Mode Description

RW RW RW RW RW

Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E

Default

1 1 1 1 0000 0000 0100

7.5.13. PHY 4 Register 26: Reserved or VLAN ID [J] Membership

7.5.13.1 PHY 4 Register 26: Reserved Register (Page=0)

Table 128. PHY 4 Register 26: Reserved Register

Reg.bit Name 26.[15:0] Reserved

Mode Description

Default 0x07D0

7.5.13.2 PHY 4 Register 26: VLAN ID [J] Membership (Page=1)

Table 129. PHY 4 Register 26: VLAN ID [J] Membership

Reg.bit Name 26.[15:5] Reserved 26.[4:0] VLAN ID [J]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN

J. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN J 10010 means port 4 and 1 are the members of VLAN J 11111 means all 5 ports are the members of VLAN J

Default 1111 1111 111 1 1111

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RTL8305SC Datasheet 7.5.14. PHY 4 Register 27: Reserved or VLAN ID [J]

7.5.14.1 PHY 4 Register 27: Reserved Register (Page=0)

Table 130. PHY 4 Register 27: Reserved Register

Reg.bit Name 27.[15:0] Reserved

Mode Description

Default

7.5.14.2 PHY 4 Register 27: VLAN ID [J] (Page=1)

Table 131. PHY 4 Register 27: VLAN ID [J]

Reg.bit Name Mode Description

27.[15:12Reserved ]

27.[11:0] VLAN ID [J] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN J

Default

1111 0000 0000 1001

7.5.15. PHY 4 Register 28: Reserved or VLAN ID [O] Membership

7.5.15.1 PHY 4 Register 28: Reserved Register (Page=0)

Table 132. PHY 4 Register 28: Reserved Register

Reg.bit Name 28.[15:0] Reserved

Mode Description

Default

7.5.15.2 PHY 4 Register 28: VLAN ID [O] Membership (Page=1)

Table 133. PHY 4 Register 28: VLAN ID [O] Membership

Reg.bit Name 28.[15:5] Reserved 28.[4:0] VLAN ID [O]

Membership Bit [4:0]

Mode Description RW

This 5-bit field specifies which ports are the members of VLAN O. If a destination address look up fails, the packet associated with this VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.:

10001 means port 4 and 0 are the members of VLAN O 10010 means port 4 and 1 are the members of VLAN O 11111 means all 5 ports are the members of VLAN O

Default 1111 1111 111 1 1111

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RTL8305SC Datasheet 7.5.16. PHY 4 Register 29: Reserved or VLAN ID [O]

7.5.16.1 PHY 4 Register 29: Reserved Register (Page=0)

Table 134. PHY 4 Register 29: Reserved Register

Reg.bit Name 29.[15:0] Reserved

Mode Description

Default

7.5.16.2 PHY 4 Register 29: VLAN ID [O] (Page=1)

Table 135. PHY 4 Register 29: VLAN ID [O]

Reg.bit Name Mode Description

29.[15:12Reserved ]

29.[11:0] VLAN ID [O] RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN O

Default

1111 0000 0000 1110

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RTL8305SC Datasheet 7.6. PHY 5 Registers 7.6.1. PHY 5 Register 0 for Port 4 MAC: Control

Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.

Table 136. PHY 5 Register 0: Control

Reg.bit Name 0.15 Reset

0.14 Loopback (digital loopback)

0.13 Speed Select

Mode Description

RO 0: No reset allowed (permanently=0) RO 0: Normal operation (permanently=0) RW

1: 100Mbps 0: 10Mbps

When NWay is enabled, this bit reflects the result of auto-negotiation (Read only).

When NWay is disabled, this bit can be set through SMI (Read/Write).

1: Enable auto-negotiation process 0: Disable auto-negotiation process

This bit can be set through SMI (Read/Write). 0: Normal operation (permanently=0) 0: Normal operation (permanently=0) 0: Normal operation (permanently=0)

Default 0 0 Pin P4SPDSTA strap option

0.12

Auto Negotiation Enable Power Down Isolate

Restart Auto Negotiation Duplex Mode

RW

Pin P4ANEG strap option

0 0 0

0.11 0.10 0.9 0.8

RO RO RO RW

0.[7:0] Reserved

1: Full duplex operation Pin

P4DUPSTA 0: Half duplex operation

strap option When NWay is enabled, this bit reflects the result of auto-negotiation (Read only).

When NWay is disabled, this bit may be set through SMI (Read/Write).

0000 0000

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RTL8305SC Datasheet 7.6.2. PHY 5 Register 1 for Port 4 MAC: Status

Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.

Table 137. PHY 5 Register 1: Status

Reg.bit Name Mode Description Default 1.15 100Base_T4 RO 0: No 100Base-T4 capability 0 1.14 100Base_TX_FD RO 1: 100Base-TX full duplex capable (permanently=1) 1 1.13 100Base_TX_HD RO 1: 100Base-TX half duplex capable (permanently=1) 1 1.12 10Base_T_FD RO 1: 10Base-TX full duplex capable (permanently=1) 1 1.11 10Base_T_HD RO 1: 10Base-TX half duplex capable (permanently=1) 1 1.[10:7] Reserved RO 0 1.6 RO The RTL8305SC will accept management frames with preamble 1 MF Preamble

Suppression suppressed (permanently=1)

1.5 RO 1: Auto-negotiation process completed. MII Reg.4, 5 are valid if 1 Auto-negotiate

Complete this bit is set (permanently=1)

1.4 Remote Fault RO 0: No remote fault (permanently=0) 0 1.3 RO 1: NWay auto-negotiation capable (permanently=1) 1 Auto-Negotiation

Ability

1.2 Link Status RO 1: Link is established Pin

P4LNKSTA# 0: Link is failed

strap option This bit reflects the status of pin P4LNKSTA# in real time.

1.1 Jabber Detect RO 0: No Jabber detected (permanently=0) 0 1.0 RO 1: Extended register capable (permanently=1) 1 Extended

Capability

7.6.3. PHY 5 Register 2 for Port 4 MAC: PHY Identifier 1

Table 138. PHY 5 Register 2: PHY Identifier 1

Reg.bit Name 2.[15:0] OUI Mode Description

RO Composed of the 3rd to 18th bits of the Organizationally Unique

Identifier (OUI), respectively

Default 0x001C

7.6.4. PHY 5 Register 3 for Port 4 MAC: PHY Identifier 2

Table 139. PHY 5 Register 3: PHY Identifier 2

Reg.bit 3.[15:10] 3.[9:4] 3.[3:0]

Name OUI

Model Number Revision Number

Mode RO RO RO

Description

Assigned to the 19th through 24th bits of the OUI

Manufacturer’s model number (05: Indicates RTL8305 Manufacturer’s revision number (02: Indicates SC

Default 1100 10 00 0101 0010

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RTL8305SC Datasheet 7.6.5. PHY 5 Register 4 for Port 4 MAC: Auto-Negotiation

Advertisement

Note: This register only works in PHY mode MII and PHY mode SNI. In MAC mode MII, these registers have no meaning.

Table 140. PHY 5 Register 4: Auto-Negotiation Advertisement

Mode Description Default RO 1: Next Page enabled 0

0: Next Page disabled (Permanently=0)

4.14 Acknowledge RO Permanently0. 0 4.13 Remote Fault RO 1: Advertises that the RTL8305SC has detected a remote fault 0

0: No remote fault detected

4.[12:11] Reserved RO 0 4.10 Pause RW 1: Advertises that the RTL8305SC possesses 802.3x flow control Pin

capability P4FLCTRL

strap option0: No flow control capability

4.9 100Base-T4 RO Technology not supported (Permanently=0) 0 4.8 100Base-TX-FD RW 1: 100Base-TX full duplex capable Pin

P4DUPSTA 0: Not 100Base-TX full duplex capable

and P4SPDSTA strap option

4.7 100Base-TX RW 1: 100Base-TX half duplex capable Pin =

P4SPDSTA 0: Not 100Base-TX half duplex capable

strap option

4.6 10Base-T-FD RW 1: 10Base-TX full duplex capable Pin

P4DUPSTA 0: Not 10Base-TX full duplex capable

or P4SPDSTA strap option

4.5 10Base-T RW 1: 10Base-TX half duplex capable 1

0: Not 10Base-TX half duplex capable

4.[4:0] Selector Field RO [00001]=IEEE 802.3 0 0001 Reg.bit 4.15

Name Next Page

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RTL8305SC Datasheet 7.6.6. MII Port NWay Mode

Table 141. MII Port NWay Mode

Event

Upon Reset

Description

Strapping P4SPDSTA=1 and P4DUPSTA=1 󰃆 Reg0.13=1, Reg0.8=1 Strapping P4SPDSTA=1 and P4DUPSTA=0 󰃆 Reg0.13=1, Reg0.8=0 Strapping P4SPDSTA=0 and P4DUPSTA=1 󰃆 Reg0.13=0, Reg0.8=1 Strapping P4SPDSTA=0 and P4DUPSTA=0 󰃆 Reg0.13=0, Reg0.8=0 Defau1t value of Reg4.10 is strapped from pin P4FLCTRL Default value of Reg1.2 is strapped from pin P4LNKSTA#

P4LNKSTA# pulled down 󰃆 Reg1.2=1 P4LNKSTA# pulled up 󰃆 Reg1.2=0

If PHY 5 register 4 is configured as Reg4.8=1, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8305SC will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=1

If PHY 5 register 4 is configured as Reg4.8=0, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8305SC will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=0

If PHY 5 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=1, Reg4.5=1, the RTL8305SC will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=1

If PHY 5 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8305SC will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0

If the CPU polls register 5, the RTL8305SC replies with the contents in register 4

If the CPU polls register 4, the RTL8305SC replies with the contents in register 4

After Reset

7.6.7. MII Port Force Mode

Table 142. MII Port Force Mode

Event

Upon Reset

Description

Strapping P4SPDSTA=1 and P4DUPSTA=1 󰃆 Reg0.13=1, Reg0.8=1 Strapping P4SPDSTA=1 and P4DUPSTA=0 󰃆 Reg0.13=1, Reg0.8=0 Strapping P4SPDSTA=0 and P4DUPSTA=1 󰃆 Reg0.13=0, Reg0.8=1 Strapping P4SPDSTA=0 and P4DUPSTA=0 󰃆 Reg0.13=0, Reg0.8=0 Defau1t value of Reg4.10 is strapped from pin P4FLCTRL Default value of Reg1.2 is strapped from pin P4LNKSTA#

P4LNKSTA# pulled down 󰃆 Reg1.2=1 P4LNKSTA# pulled up 󰃆 Reg1.2=0

The CPU only writes register 0.13 and 0.8 to propose a link configuration, then reads register 1.2 to determine whether the link partner can accept this link configuration

After Reset

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RTL8305SC Datasheet 8. Functional Description

8.1. Switch Core Functional Overview 8.1.1. Applications

The RTL8305SC is a 5-port Fast Ethernet switch controller that integrates memory, five MACs, and five physical layer transceivers for 10Base-T and 100Base-TX operation into a single chip. All ports support 100Base-FX, which shares pins (TX+-/RX+-) with UTP ports and needs no SD+/- pins, a development using Realtek proprietary technology. To compensate for the lack of auto-negotiation in 100Base-FX applications, the RTL8305SC can be forced into 100Base-FX half or full duplex mode, and can enable or disable flow control in fiber mode.

The five ports are separated into three groups (GroupX/GroupY/Port4) for flexible port configuration using strapping pins upon reset. The SetGroup pin is used to select the port numbers for GroupX and GroupY (SetGroup=1: GroupX = Port0; GroupY = Ports 1, 2, and 3. SetGroup=0: GroupX = Ports 0 and 1; GroupY = Ports 2 and 3). The GxMode/GyMode/P4Mode[1:0] pins are used to select the operation mode (UTP/FX for GroupX and GroupY, UTP/FX/PHY mode MII/PHY mode SNI/MAC mode MII for Port 4). Upon reset, in addition to using strapping pins, the RTL8305SC can be configured with an EEPROM or read/write operation by a CPU via the MDC/MDIO interface.

For more detailed system application circuits, refer to Application Information, page 141. Note:

Upon Reset: Defined as a short time after the end of a hardware reset. After Reset: Defined as the time after the specified ‘Upon Reset’ time.

8.1.2. Port 4

Operating Mode of Port 4

Each port has two parts: MAC and PHY. In UTP and FX mode, Port 4 uses both the MAC and internal PHY parts like the other ports. In other modes, Port 4 uses only the MAC part, which provides an external interface to connect to the external MAC or PHY. Two pins are used for these operation mode configurations: P4MODE[1:0].

Port 4 supports an external MAC interface which can be set to PHY mode MII, PHY mode SNI, or MAC mode MII to work with the external MAC of a routing engine, PHY of a HomePNA, or other physical layer transceiver.

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RTL8305SC Datasheet If the MAC part of Port 4 connects with an external MAC, such as the processor of a router application, it will act as a PHY. This is PHY mode MII, or PHY mode SNI. In PHY mode MII or PHY mode SNI, Port 4 uses the MAC part only, and provides an external MAC interface to connect MACs of external devices. In order to connect both MACs, the MII of the switch MAC should be reversed into PHY mode. If the MAC part of Port 4 connects with an external PHY, such as the PHY of a HomePNA application, Port 4 will act as a MAC. This is MAC mode MII. In MAC mode MII, Port 4 uses its MAC to connect to an external PHY and ignores the internal PHY part. External MAC Interface

In order to act as a PHY when Port 4 is in PHY mode, some pins of the external MAC interface must be changed. For example, TXC are input pins for MAC, but output pins for PHY. The MTXC/PRXC pin is input for MAC mode and output for PHY mode. Refer to Figure 3, page 93 to check the relationship between the RTL8305SC and the external device.

Tip: Connect the input of the RTL8305SC to the output of the external device. The RTL8305SC has no RXER, TXER, and CRS pins for MII signaling. Because the RTL8305SC does not support pin CRS, it is necessary to connect the MTXEN/PRXDV (output) of PHY mode to both CRS and RXDV (input) of the external device. Port 4 Status Pins

When P4MODE[1:0]=11, Port 4 can be either UTP or MAC mode MII. Port 4 will automatically detect the link status of UTP from the internal PHY, and the link status of MAC mode MII from both the TXC of the external PHY and from P4LNKSTA#. If both UTP and MII port are linked OK, UTP has higher priority and the RTL8305SC will ignore the signal of the MII port.

In UTP and FX mode, the internal PHY will provide the port status (Link/Speed/Duplex/Full Flow Control ability) in real time. In order to provide the initial configuration of Port 4’s PHY (UTP or FX mode), four pins (P4ANEG, P4Full, P4Spd100, P4EnFC) are used to strap upon reset. However, three of these pins are also used for Port 4’s MAC (the other three modes) in real time after reset (P4Spd100 -> P4SpdSta, P4Full -> P4DupSta, P4EnFC -> P4FLCTRL).

In the other three modes, four pins (P4LNKSTA#, P4SpdSta, P4DupSta, P4FLCTRL) are necessary in order to provide the port status to Port 4’s MAC. That means that the external MAC or PHY should be forced to the same port status as Port 4’s MAC.

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RTL8305SC Datasheet Related Pins

When Port 4 is in UTP or FX mode, the LEDs of Port 4 are used to display PHY status. When Port 4 is in other modes, the LEDs of Port 4 are used to display MAC status.

Four parallel LEDs corresponding to port 4 can be tri-stated (disable LED functions) for MII port application by setting ENP4LED in EEPROM to 0. In UTP applications, this bit should be 1.

The SEL_MIIMAC# pin can be used to indicate MII MAC port active after reset for the purposes of UTP/MII auto-detection.

One 25MHz clock output (pin CK25MOUT) can be used as a clock source for the underlying HomePNA/other PHY physical devices. PHY Mode MII/PHY Mode SNI

In routing applications, the RTL8305SC cooperates with a routing engine to communicate with the WAN (Wide Area Network) through MII/SNI. In such applications, P4LNKSTA# =0 and P4MODE[1] is pulled low upon reset. P4MODE[0] determines whether MII or SNI mode is selected.

In MII (nibble) mode (P4MODE[0]=1), P4SPDSTA=1 results in MII operating at 100Mbps with MTXC, and MRXC runs at 25MHz; however, P4SPDSTA=0 leads to MII operating at 10Mbps with MTXC, and MRXC runs at 2.5MHz.

In SNI (serial) mode (P4MODE[0]=0), P4SPDSTA has no effect and should be pulled-down. SNI mode operates at 10Mbps only, with MTXC and MRXC running at 10MHz. In SNI mode the RTL8305SC does not loopback an RXDV signal as a response to TXEN, and does not support the heartbeat function (asserting COL signal for each complete TXEN signal).

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RTL8305SC Datasheet Floating=HighFloating=High44-P4MODE[1]45-P4MODE[0]60-MRXDV/PTXENPull Down=Link OnNote 1Note 2Note 3LED Indication49-P4LNKSTA#47-P4SPDSTA/P4FULL48-P4DUPSTA/P4SPD10067~61-MRXD[3:0]/PTXD[3:0]51-MTXC/PRXC52-MTXEN/PRXDV4459-MRXC/PTXCRXCCRSRXDVRXD[3:0]TXCTXENTXDCOLVDSL/HomePNA/Single PHY46-P4FLCTRL/P4ENFC57~54-MTXD[3:0]/PRXD[3:0]68-SELMIIMAC#/DISDSPRI58-MCOL/PCOLMAC Mode MII

Pull DownFloating=High51-MTXC/PRXC44-P4MODE[1]45-P4MODE[0]52-MTXEN/PRXDV57~54-MTXD[3:0]/PRXD[3:0]Pull Down=Link OnNote 1Note 2Note 349-P4LNKSTA#47-P4SPDSTA/P4FULL48-P4DUPSTA/P4SPD10046-P4FLCTRL/P4ENFC59-MRXC/PTXC60-MRXDV/PTXEN67~61-MRXD[3:0]/PTXD[3:0]58-MCOL/PCOL44CRSRXDVRXD[3:0]TXCTXENTXDCOL25MHzRXC

CPU/Processor/RoutingEnginePHY Mode MII

Pull Down51-MTXC/PRXC44-P4MODE[1]45-P4MODE[0]52-MTXEN/PRXDV54-MTXD[0]/PRXD[0]Pull Down=Link OnNote 1Note 2Note 349-P4LNKSTA#47-P4SPDSTA/P4FULL48-P4DUPSTA/P4SPD10046-P4FLCTRL/P4ENFC59-MRXC/PTXC60-MRXDV/PTXEN61-MRXD[0]/PTXD[0]58-MCOL/PCOLCRSRXDVRXDTXCTXENTXDCOL10MHzRXC

CPU/Processor/RoutingEnginePHY Mode SNI

Figure 3. Port 4 Operating Mode Overview

Note 1: Pulled high or floating to set speed to 100Mbps, and pulled low to set speed to 10Mbps. Note 2: Pulled high or floating to set to full duplex, and pulled low to set to half duplex.

Note 3: Pulled high or floating to enable flow control in full duplex, and pulled low to disable.

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RTL8305SC Datasheet MAC Mode MII

In HomePNA or other PHY applications, the RTL8305SC provides the MII interface to the underlying HomePNA or other physical device in order to communicate with other types of LAN media. In such applications, the P4MODE[1:0] pins are floating upon reset and the RTL8305SC supports the UTP/MII auto-detection function. When both UTP and MII are active (link on), the UTP port has higher priority than the MII port.

In HomePNA applications P4SPDSTA must be pulled down, as HomePNA is half-duplex only. P4DUPSTA should also be pulled down. P4LNKSTA# must be pulled down instead of being wired to the LINK LED pin of the HomePNA because of the unstable link state of HomePNA, a characteristic of the HomePNA 1.0 standard.

Because the HomePNA PHY physical layer is half duplex and can only detect a collision event during the AID header interval (the time when transmitting the Ethernet preamble), the back pressure flow control algorithm is not suitable for the HomePNA network and the P4FLCTRL pin should be pulled down. For other PHY applications, P4SPDSTA, P4DUPSTA, and P4FLCTRL depend on the application.

8.1.3. Port Status Configuration

The RTL8305SC supports flexible port status configuration for PHY by pin (GxANeg/GyANeg/P4ANeg, GxSpd100/ GySpd100/P4Spd100, and GxFull/GyFull/P4Full) on a group basis upon reset, or by internal registers (Reg0.12, Reg0.13, Reg0.8, and Reg4.5/4.6/4.7/4.8) via SMI on a per-port basis after reset. Those pins are used to assign the initial value of MII register 0 and 4 (PHY registers) upon reset. The registers can be updated via SMI on a per-port basis after reset. For example, the initial value of register 0.12 of Port 4 will be 0 when pin P4Aneg is 1 upon reset.

All ports support 100Base-FX, which shares pins with UTP (TX+-/RX+-) and needs no SD+- pins (Realtek patent). 100Base-FX can be forced into half or full duplex mode with optional flow control ability. In order to operate correctly, both sides of the connection should be set to the same settings. In 100Base-FX, duplex and flow control ability can be set via strapped pins upon reset, or via SMI after reset.

Note: In compliance with IEEE 802.3u, 100Base-FX does not support Auto-Negotiation.

Pins GxANeg/GyANeg/P4Aneg as well as GxSpd100/GySpd100/P4Spd100 are not used for 100Base-FX mode and can be left floating while in 100Base-FX mode. For example, Port 4 will be forced into full duplex 100Base-FX with flow control ability when P4Mode[1:0]=10, P4Full=1, P4EnFC=1 upon reset (regardless of P4Spd100 and P4ANeg).

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RTL8305SC Datasheet When Auto-Negotiation ability is enabled in UTP mode, the RTL8305SC supports Auto-Negotiation and parallel detection of 10Base-T/100Base-TX to automatically determine line speed, duplex, and flow control. The parallel detection process is used when connecting a device that does not support auto-negotiation.

For example: port0 is UTP with all abilities (default for normal switch applications: GxMode=1, GxANeg=1, GxSpd100=1, GxFull=1, GxEnFC=1. The content of MII registers will be Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and Reg4.10=1). If the connecting device supports auto-negotiation, 10Full with 802.3x flow control ability, port0 will enter the auto-negotiation process. The result will be 10Full with 802.3x flow control ability for both devices. If the other device is 10M without auto-negotiation, port0 will enter the parallel detection process. The result will be 10Half without 802.3x flow control ability for port0.

Note: Each port can operate at 10Mbps or 100Mbps in full-duplex or half-duplex mode independently of others when auto-negotiation is on.

The port status for the PHY on a group basis can easily be set by pin configuration. For example, when group X is 100FX (GxMode=0), group X can be set as force mode half duplex by setting pin GxFull to 0. Group Y can also be set as UTP mode NWAY mode 10Full by setting GyMode=1, GyANeg=1, GySpd100=0, GyFull=1. Refer to section 5 Pin Descriptions for details.

8.1.4. Flow Control

The RTL8305SC supports IEEE 802.3x full duplex flow control, Force mode Full duplex Flow Control, and optional half duplex back pressure. IEEE 802.3x Full Duplex Flow Control

For UTP with auto-negotiation ability (GxANeg/GyANeg/P4Aneg set to 1), the pause ability (Reg.4.10) of full duplex flow control is enabled by pins GxEnFC/GyEnFC/P4EnFC on a group basis upon reset, or internal registers via SMI on a per-port basis after reset. For UTP with auto-negotiation ability, IEEE 802.3x flow control’s ability is auto-negotiated between the remote device and the RTL8305SC. If the auto-negotiation result of the 802.3x pause ability is ‘Enabled’ (Reg.4.10=1 and Reg.5.10=1), the full duplex 802.3x flow control function is enabled. Otherwise, the full duplex 802.3x flow control function is disabled.

Force Mode Full Duplex Flow Control

For UTP without auto-negotiation ability (GxANeg/GyANeg/P4Aneg is 0) and 100Base-FX, IEEE 802.3x flow control’s ability can be forced to ‘Enabled’ by pins GxEnFC/GyEnFC/P4EnFC on a group basis upon reset, or internal registers (Reg.5.10) via SMI on a per-port basis after reset. For

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RTL8305SC Datasheet example, port 4 will be forced to 10Full UTP with forced mode full duplex flow control ability, regardless of the connected device, when P4Mode[1:0]=10, P4Aneg=0, P4Spd100=0, P4Full=1, P4EnFC=1. Port 0 will be forced to 100Full FX with forced mode full duplex flow control ability, regardless of the connected device, when SetGroup=1, GxMode=0, GxFull=1, GxEnFC=1.

Regardless of IEEE 802.3x full duplex flow control or Force mode Full duplex Flow Control, when full duplex flow control is enabled, the RTL8305SC will only recognize the 802.3x flow control PAUSE ON/OFF frames with DA=0180C2000001, type = 8808, OP-code=01, PAUSE Time = maximum to zero, and with a good CRC.

If a PAUSE frame is received from any PAUSE flow control enabled port set to DA=0180C2000001, the corresponding port of the RTL8305SC will stop its packet transmission until the PAUSE timer times out or another PAUSE frame with zero PAUSE time is received. The RTL8305SC will not forward any 802.3x PAUSE frames received from any port. Half Duplex Back Pressure

If pin EnDefer is 1, the RTL8305SC will send a preamble to defer the other station’s transmission when there is no packet to send. Otherwise, if pin EnDefer is 0, the RTL8305SC will force a collision with the other station’s transmission when the buffer is full.

If pin 48pass1 is 0, the RTL8305SC will always collide with JAM (Continuous collision). Otherwise, if pin 48pass1 is 1, the RTL8305SC will try to forward one packet successfully after 48 forced collisions (48pass1), to avoid the connected repeater being partitioned due to excessive collisions. NWay Mode

For UTP with auto-negotiation ability, pins GxEnFC/GyEnFC/P4EnFC are effective only in full duplex mode. Therefore, for UTP in half duplex mode, half duplex back pressure flow control is controlled by the ENBKPRS pin strap upon hardware reset. Force Mode

For UTP without auto-negotiation ability, or in 100Base-FX mode, the operation mode can be forced to half duplex. Half duplex back pressure flow control can be forced to ‘enabled’ on the RTL8305SC side by pin GxEnFC/GyEnFC/P4EnFC on a group basis upon reset.

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RTL8305SC Datasheet 8.1.5. Address Search, Learning, and Aging

When a packet is received, the RTL8305SC will use the least 10 bits of the destination MAC address to index the 1024-entry lookup table, and at the same time will compare the destination MAC address with the contents of the 16-entry CAM. If the indexed entry is valid, or the CAM comparison is matched, the received packet will be forwarded to the corresponding destination port. Otherwise, the RTL8305SC will broadcast the packet. This is the ‘Address Search’.

The RTL8305SC then extracts the least 10 bits of the source MAC address to index the 1024-entry lookup table. If the entry is not already in the table it will record the source MAC address and add switching information. If this is an occupied entry, it will update the entry with new information. This is called ‘Learning’. If the indexed location has been occupied by a different MAC address (hash collision), the new source MAC address will be recorded into the 16-entry CAM. The 16-entry CAM reduces address hash collisions and improves switching performance.

Address aging is used to keep the contents of the address table correct in a dynamic network topology. The lookup engine will update the time stamp information of an entry whenever the corresponding source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not refreshed by the address learning process during the aging time period. The aging time of the RTL8305SC is between 200 and 300 seconds.

8.1.6. Address Direct Mapping Mode

The RTL8305SC uses the least 10 bits of the MAC address to index the 1024-entry lookup table. For example: the index of MAC address ‘12 34 56 78 90 ab’ will be 0xab.

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RTL8305SC Datasheet 8.1.7. Half Duplex Operation

In half duplex mode, the CSMA/CD media access method is the means by which two or more stations share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If the message collides with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure propagation of the collision throughout the system. The station remains silent for a random amount of time (backoff) before attempting to transmit again.

When a transmission attempt has terminated due to a collision, it is retried until it is successful. A controlled randomization process called ‘truncated binary exponential backoff’ determines the scheduling of the retransmissions. At the end of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. The delay is an integer multiple of slotTime (512 bit times). The number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer ‘r’ in the range: 0 ≤ r < 2k where:

k = min (n, backoffLimit). IEEE 802.3 defines the backoffLimit as 10.

8.1.8. InterFrame Gap

The InterFrame Gap is 9.6µs for 10Mbps Ethernet and 960ns for 100Mbps Fast Ethernet.

8.1.9. Illegal Frame

Illegal frames such as CRC error packets, runt packets (length < 64 bytes), and oversize packets (length > maximum length), will be discarded.

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RTL8305SC Datasheet 8.1.10. Dual MII Interface

Home Gateways, broadband access routers, and SOHO routers generally contain a powerful Network Processor, with many I/O interfaces, including MII and SNI interfaces. Traditionally, this system connects one of the MII interfaces to a single PHY as the WAN port, and another interface connects to a multi-port switch as the LAN ports. In order to meet application demands, Realtek offers an advanced dual MII interface for this application. This eliminates the need for a single PHY.

Figure 4 shows the traditional design of a SOHO router. In this case, the router needs an extra single PHY as the WAN port. A traditional 5-port switch has five MAC and five PHY circuits on a single chip. When port 4 is configured as MII-MAC/MII-PHY/SNI-PHY, we only use the MAC part of port 4.

5 Port SwitchSwitch CoreP0MACP1MACP2MACP3MACP4MACP4_MIIMII_1MII_2P0PHYP1PHYP2PHYP3PHYP4PHYSinglePHYCPUwith Dual MIILANWAN

Figure 4. Traditional Application

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 99 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet The RTL8305SC has pin 42, DISDUALMII, to support both port 4 PHY and MAC circuits. When the Dual MII feature is enabled, the port 4 PHY may be used as the WAN interface as shown in Figure 5.

RTL8305SCSwitch CoreP0MACP1MACP2MACP3MACP4MACP4_MIIP2_MIIP0PHYP1PHYP2PHYP3PHYP4PHYMII_1MII_2CPUwith Dual MIILAN

WAN

Figure 5. Dual MII Application Diagram

Dual MII Interfaces Configuration

Port 4 of the RTL8305SC is able to separate the MAC and PHY circuits via the DISDUALMII configuration. When DISDUALMII is configured as 0, the port 4 MAC circuit supports MAC mode MII, PHY mode MII, or PHY mode SNI interface. The port 4 PHY circuit supports an MII on the MAC side, and a UTP or fiber interface in the PHY transceiver. Four pins define the mode of the dual MII interface, DISDUALMII (pin-42), P4MODE[0] (pin-45), P4MODE[1] (pin-44), and P4PHY_MODE (pin-68). • DISDUALMII: Enable dual MII interface feature, pull high = disable, and pull low = enable. • P4MODE[1:0]: When DISDUALMII is enabled: 11b/10b = P4MAC is MAC mode MII 01b = P4MAC is PHY mode MII 00b = P4MAC is PHY mode SNI • P4PHY_MODE: When DISDUALMII is enabled: 1b = P4PHY is UTP mode 0b = P4PHY is Fiber mode

The following figures show the four types of configuration for the RTL8305SC with a CPU application.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 100 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet MAC Mode MII Interface

Floating=HighFloating=HighFloating=High44-P4MODE[1]45-P4MODE[0]68-P4PHY_MODEPHY Mode MII Interface

MAC1_TXCMAC1_CRSMAC1_TXEN4MAC1_TXD[3:0]MAC1_RXCMAC1_RXDV4MAC1_RXD[3:0]MAC1_COLRTL8305SC51-MTXC/PRXC52-MTXEN/PRXDV57~54-MTXD[3:0]/PRXD[3:0]59-MRXC/PTXC60-MRXDV/PTXEN67~66, 63~61-MRXD[3:0]/PTXD[3:0]58-MCOL/PCOL10K ohm10K ohm42-DISDUALMII49-P4LNKSTA#User Defined47-P4SPDSTA81-PHY2RXCMAC2_RXCMAC2_CRSCPU/Processor/Routing EngineUser DefinedUser Defined48-P4DUPSTA46-P4FLCTRL80-PHY2RXDV78~76, 73-PHY2RXD[3:0]82-PHY2TXC83PHY2TXEN88, 86~84-PHY2TXD[3:0]89-PHY2COL44MCA2_RXDVMAC2_RXD[3:0]MAC2_TXCMAC2_TXENMAC2_TXD[3:0]MAC2_COLPHY Mode MII InterfaceMAC Mode MII Interface

Figure 6. Dual MII Mode with 1 MII-MAC + 1 MII-PHY (100Base-T UTP) Interfaces Application Circuit

MAC Mode MII Interface

Irrelevant44-P4MODE[1]45-P4MODE[0]68-P4PHY_MODEPHY Mode MII Interface

MAC1_TXCMAC1_CRSRTL8305SC51-MTXC/PRXC52-MTXEN/PRXDVIrrelevant10K ohmMAC1_TXEN4MAC1_TXD[3:0]MAC1_RXCMAC1_RXDV4MAC1_RXD[3:0]MAC1_COL57~54-MTXD[3:0]/PRXD[3:0]59-MRXC/PTXC60-MRXDV/PTXEN67~66, 63~61-MRXD[3:0]/PTXD[3:0]58-MCOL/PCOL10K ohm10K ohm42-DISDUALMII49-P4LNKSTA#User Defined47-P4SPDSTA/P4FULL81-PHY2RXCMAC2_RXCMAC2_CRSCPU/Processor/Routing EngineUser DefinedUser Defined48-P4DUPSTA/P4SPD10046-P4FLCTRL/P4ENFC80-PHY2RXDV78~76, 73-PHY2RXD[3:0]82-PHY2TXC83-PHY2TXEN88, 86~84-PHY2TXD[3:0]89-PHY2COL44MCA2_RXDVMAC2_RXD[3:0]MAC2_TXCMAC2_TXENMAC2_TXD[3:0]MAC2_COLPHY Mode MII Interfaceof 100Base-FX Mode

MAC Mode MII Interface

Figure 7. Dual MII Mode with 1 MII-MAC + 1 MII-PHY (100Base-FX Mode) Interfaces Application Circuit

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101 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet

PHY Mode MII Interface 1

10K ohm44-P4MODE[1]Floating=HighFloating=High10K ohm10K ohmMAC Mode MII Interface 1

MAC1_RXCMAC1_CRSMAC1_RXDV4MAC1_RXD[3:0]MAC1_TXCMAC1_TXEN4MAC1_TXD[3:0]MAC1_COLRTL8305SC51-MTXC/PRXC52-MTXEN/PRXDV45-P4MODE[0]68-P4PHY_MODE42-DISDUALMII49-P4LNKSTA#57~54-MTXD[3:0]/PRXD[3:0]59-MRXC/PTXC60-MRXDV/PTXEN67~66, 63~61-MRXD[3:0]/PTXD[3:0]58-MCOL/PCOLUser Defined47-P4SPDSTA81-PHY2RXCMAC2_RXCMAC2_CRSCPU/Processor/Routing EngineUser DefinedUser Defined48-P4DUPSTA46-P4FLCTRL80-PHY2RXDV78~76, 73-PHY2RXD[3:0]82-PHY2TXC83-PHY2TXEN88, 86~84-PHY2TXD[3:0]89-PHY2COL44MCA2_RXDVMAC2_RXD[3:0]MAC2_TXCMAC2_TXENMAC2_TXD[3:0]MAC2_COLPHY Mode MII Interface 2MAC Mode MII Interface 2

Figure 8. Dual MII Mode with 1 MII-PHY + 1 MII-PHY (100Base-T UTP) Interfaces Application Circuit

PHY Mode SNI Interface

10K ohm44-P4MODE[1]10K ohm45-P4MODE[0]Floating=High10K ohm42-DISDUALMII10K ohm10K ohm47-P4SPDSTAUser DefinedUser Defined81-PHY2RXCMAC2_RXCMAC2_CRS46-P4FLCTRL80-PHY2RXDV78~76, 73-PHY2RXD[3:0]82-PHY2TXC83-PHY2TXEN88, 86~84-PHY2TXD[3:0]89-PHY2COL44MCA2_RXDVMAC2_RXD[3:0]MAC2_TXCMAC2_TXENMAC2_TXD[3:0]MAC2_COL49-P4LNKSTA#68-P4PHY_MODE52-MTXEN/PRXDV54-MTXD[0]/PRXD[0]59-MRXC/PTXC60-MRXDV/PTXEN61-MRXD[0]/PTXD[0]58-MCOL/PCOLMAC Mode SNI Interface

MAC1_RXCMAC1_CRSMAC1_RXDVMAC1_RXDMAC1_TXCMAC1_TXENMAC1_TXDMAC1_COLRTL8305SC51-MTXC/PRXCCPU/Processor/Routing Engine48-P4DUPSTAPHY Mode MII Interface

MAC Mode MII Interface

Figure 9. Dual MII Mode with 1 SNI-PHY + 1 MII-PHY (100Base-T UTP) Interfaces Application Circuit

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

102 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Dual MII Registers Definition

For RTL8305SC single MII interface applications (DISDUALMII=1), PHY 5 MII registers represent the Port 4 MAC part.

For RTL8305SC dual MII interface applications (DISDUALMII=0), PHY4 registers represent the Port 4 PHY part (Read/Write), and PHY5 registers represent the Port 4 MAC part (Reg.013, 0.12, 0.8, 4.10, 4.8~4.5 are Read/Write; others are Read-Only). The 100Base-FX mode of the PHY circuit (P4MODE[1:0]=10) only supports 100Mbps and full duplex. The PHY circuit of UTP mode only supports full ability NWay (Flow control enabled, both 10/100Mbps, both Full/Half duplex).

The RTL8305SC support four status pins to provide the link status or initial configuration for the MAC circuit. A brief description of the function follows: • • • •

Table 143 shows the MII PHY registers of PHY4 and PHY5 definitions when P4MODE[1:0] and DISDUALMII are configured in various combinations.

Table 143. MII Register Definition for PHY 4 and PHY 5

Dis P4MODE Port 4 Mode PHY4 (Single Mode MII) DualMII [1:0] (Reg0, 1, 2, 3, 4, 5)

1 11 Reset: P4LNKSTA#=1 UTP Upon or Reg. 0.13=P4SPDSTA P4LNKSTA#=0 Reg. 0.12=P4ANEG but UTP link Reg. 0.8=P4DUPSTA on: Reg. 1.2=Signal detection and

latch low

Reg. 4.10=P4FLCTRL Reg. 4.8~4.5= Reg. P4 P4 4.8~4.5SPDSTADUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0 Reg. 5.10=NWay result Reg. 5.8~5.5=NWay result

After Reset:

All RW pins should be fully configurable and act as standard.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

P4LNKSTA#: Determines the link status of Port 4 MAC in real-time

P4SPDSTA: Provides initial configuration pin for speed ability upon reset P4DUPSTA: Provides initial configuration pin for duplex ability upon reset

P4FLCTRL: Provides initial configuration pin for flow control ability upon reset

PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5)

N/A UTP 103 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

P4LNKSTA#=0 MAC:

and UTP link MAC off: mode

MII PHY: N/A UTP: N/A

1 10 MAC: N/A

PHY: N/A

UTP: 100Base-FX (Fiber)

PHY4 (Single Mode MII) PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5) (Reg0, 1, 2, 3, 4, 5)

N/A Upon Reset: Port 4

MACReg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5.

N/A Fiber Upon Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=0 (NWay=Disable) Reg. 0.8=P4DUPSTA Reg. 1.2=Signal detection Reg. 4.10=P4FLCTRL Reg. 4.8~4.5=1111 Reg. 5.10=Reg. 4.10

Reg. 5.8~5.5= Reg. 4.8~4.5

After Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=0 (NWay=Disable) Reg. 0.8=Configurable Reg. 1.2=Signal detection Reg. 4.10=Configurable Reg. 4.8~4.5=1111 Reg. 5.10=Reg. 4.10

Reg. 5.8~5.5=Reg. 4.8~4.5

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

1 01 MAC: PHY mode MII

PHY: N/A UTP: N/A

PHY4 (Single Mode MII) PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5) (Reg0, 1, 2, 3, 4, 5)

N/A Upon Reset: Port 4

MACReg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5= Keep the contents identical to Reg. 4.10 and 4.8~4.5.

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

1 00 MAC: PHY mode SNI

PHY: N/A UTP: N/A

PHY4 (Single Mode MII) PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5) (Reg0, 1, 2, 3, 4, 5)

N/A Upon Reset: Port 4

MACReg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5= Keep the contents identical to Reg. 4.10 and 4.8~4.5.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller 106 Track ID: JATR-1076-21 Rev. 1.2

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

0 11 P4PHY_MODE (pin

68)=1

MAC: MAC mode MII PHY: PHY mode MII UTP: 100Base-TX

PHY4 (Single Mode MII) (Reg0, 1, 2, 3, 4, 5) Upon Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=1 (NWay=Enable) Reg. 0.8=1 (Duplex=Full) Reg. 1.2=Signal detection and latch low

Reg. 4.10=1 (Enable Fctrl) Reg. 4.8~4.5=1111

Reg. 5.10=Depends on NWay result

Reg. 5.8~5.5=Depends on NWay result

After Reset:

All RW pins should be fully configurable and act as standard.

PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5)

Upon Reset: Port 4

PHY Reg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

0 10 P4PHY_MODE

(pin 68)=0

MAC: MAC mode MII PHY: PHY mode MII UTP: 100Base-FX (Fiber)

PHY4 (Single Mode MII) (Reg0, 1, 2, 3, 4, 5) Upon Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=0 (NWay=Disable) Reg. 0.8=1 (Duplex=Full) Reg. 1.2=Signal detection and latch low

Reg. 4.10=1 (Enable Fctrl) Reg. 4.8~4.5=1111 Reg. 5.10=1

Reg. 5.8~5.5=1111

After Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=0 (NWay=Disable) Reg. 0.8=Configurable Reg. 1.2=Signal detection Reg. 4.10=Configurable Reg. 4.8~4.5=1111 Reg. 5.10=Reg. 4.10 Reg. 5.8~5.5=1111

PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5)

Upon Reset: Fiber Reg. 0.13=P4SPDSTA Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

0 01 MAC: PHY mode MII

PHY: PHY mode MII UTP: 100Base-TX

PHY4 (Single Mode MII) (Reg0, 1, 2, 3, 4, 5) Upon Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=1 (NWay=Enable) Reg. 0.8=1 (Duplex=Full) Reg. 1.2=Signal detection and latch low

Reg. 4.10=1 (Enable Fctrl) Reg. 4.8~4.5=1111

Reg. 5.10=Depends on NWay result

Reg. 5.8~5.5=Depends on NWay result

After Reset:

All RW pins should be fully configurable and act as standard.

PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5)

Upon Reset: Port 4

PHY Reg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5

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RTL8305SC Datasheet Dis P4MODE Port 4 Mode DualMII [1:0]

0 00 MAC: PHY mode SNI

PHY: PHY mode MII UTP: 100Base-TX

PHY4 (Single Mode MII) (Reg0, 1, 2, 3, 4, 5) Upon Reset:

Reg. 0.13=1 (Speed=100M) Reg. 0.12=1 (NWay=Enable) Reg. 0.8=1 (Duplex=Full) Reg. 1.2=Signal detection and latch low

Reg. 4.10=1 (Enable Fctrl) Reg. 4.8~4.5=1111

Reg. 5.10=Depends on NWay result

Reg. 5.8~5.5=Depends on NWay result

After Reset:

All RW pins should be fully configurable and act as standard.

PHY5 Port 4

LED (Reg0, 1, 2, 3, 4, 5)

Upon Reset: Port 4

PHY Reg. 0.13=P4SPDSTA

Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg. 1.2=P4LNKSTA# Reg. 4.10=P4FLCTRL Reg. 5.10=P4FLCTRL

Reg. 4.8~4.5=Reg. 5.8~5.5= Reg. P4 P4 4.8~4.5 SPDSTA DUPSTA1111 1 1 0111 1 0 0011 0 1 0001 0 0

After Reset:

Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable

Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5

8.2. Physical Layer Functional Overview 8.2.1. Auto-Negotiation for UTP

The RTL8305SC obtains the states of duplex, speed, and flow control ability for each port in UTP mode through the auto-negotiation mechanism defined in the IEEE 802.3u specifications. During auto-negotiation, each port advertises its ability to its link partner and compares its ability with advertisements received from its link partner. By default, the RTL8305SC advertises full capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability.

8.2.2. 10Base-T Transmit Function

The output 10Base-T waveform is Manchester-encoded before it is driven into the network media. The internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external filter.

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RTL8305SC Datasheet 8.2.3. 10Base-T Receive Function

The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is above squelch level.

8.2.4. Link Monitor

The 10Base-T link pulse detection circuit continually monitors the RXIP/RXIN pins for the presence of valid link pulses. Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs.

8.2.5. 100Base-TX Transmit Function

The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly.

The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit stream is driven into the network media in the form of MLT-3 signaling. The MLT-3 multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also reduces EMI emissions.

8.2.6. 100Base-TX Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error rate. A De-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL circuit. Finally, the converted parallel data is fed into the MAC.

8.2.7. 100Base-FX

All ports support 100Base-FX, which shares pins with UTP (TX+-/RX+-) and needs no SD+- pins. 100Base-FX can be forced to half or full duplex with optional flow control ability.

Note: In compliance with IEEE 802.3u, 100Base-FX does not support Auto-Negotiation. In order to operate correctly, both sides of the connection should be set to the same duplex and flow control ability.

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RTL8305SC Datasheet A scrambler is not needed in 100Base-FX. Compared to common 100Base-FX applications, the RTL8305SC removes a pair of differential SD (Signal Detect) signals that provide a link monitoring function, which reduces the pin count (Realtek patent).

8.2.8. 100Base-FX Transmit Function

In 100Base-FX transmission, di-bits of TXD are processed as 100Base-TX except without being scrambled before the NRZI stage. Instead of converting to MLT-3 signals as in 100Base-TX, the serial data stream is driven out as NRZI PECL (Positive Emitter Coupled Logic) signals, which enter the fiber transceiver in differential-pairs form. The fiber transceiver may be 3.3V or 5V capable. Refer to 100Base-FX Application, on page 143 for an example application.

Table 144. PECL DC Characteristics

Parameter

PECL Input High Voltage PECL Input Low Voltage PECL Output High Voltage PECL Output Low Voltage

Symbol Min Vih Vdd-1.16 Vil Vdd-1.81 Voh Vdd-1.02 Vol Max Unit

Vdd-0.88 V Vdd-1.47 V

V

Vdd-1.62 V

8.2.9. 100Base-FX Receive Function

Signals are received through Positive Emitter Coupled Logic (PECL) receiver inputs from a fiber transceiver and directly passed to a clock recovery circuit for data/clock recovery. Scrambling/de-scrambling is bypassed in 100Base-FX.

8.2.10. 100Base-FX FEFI

When 100FX is enabled, PHY Reg.1.4 (Remote Fault) is the Far-End-Fault-Indicator (FEFI) bit for ports, and indicates that a FEFI has been detected. The FEFI is an alternative in-band signaling that is composed of 84 consecutive 1’s followed by one 0. When the RTL8305SC has detected this pattern three times, Reg.1.4 will be set, which means the transmit path (Remote side’s receive path) has problems. On the other hand, to send an FEFI stream pattern, the following condition needs to be satisfied; the incoming signal causes link failure, which in turn causes the remote side to detect a Far-End-Fault. This means that the receive path has a problem from the view of the RTL8305SC. The FEFI mechanism is used only in 100Base-FX.

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RTL8305SC Datasheet During detection of the FEFI, PHY Reg.1.4 should be set to 1. It should remain 1, even after it is read, as long as FEFI is continuously detected by the RTL8305SC. PHY Reg.1.4 should not be cleared until the FEFI has disappeared.

If there is no FEFI, then PHY Reg.1.4 should be 0. In normal conditions where there is no optical or electrical input signal; OPT-PHY should not detect Far-End-Fault signals since there is no such signal at the optical input.

When Optical Receiving Fiber is disconnected from RTL8305SC, the FEFI cannot be detected by the RTL8305SC and also cannot be reflected on PHY Reg.1.4 since there is no FEFI. If there is a FEFI before Optical Receiving Fiber is disconnected, Reg.1.4 should be kept on 1. This bit should be cleared to 0 after it is read (read and clear).

The OPT-PHY of RTL8305SC will not reflect the FEFI (Reg.1.4=1) when Optical Fiber is disconnected at power up, in spite of No-Far-End-Fault signals. After power on, the default value of PHY Reg1.4 will appear as ‘0’.

8.2.11. Reduced Fiber Interface

The RTL8305SC ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is achieved by monitoring RD signals from the fiber transceiver and checking whether any link integrity events are met. This significantly reduces pin-count, especially for high-port PHY devices. This is a Realtek patent-pending technology and available only with Realtek product solutions.

8.2.12. Power Saving Mode

The RTL8305SC implements power saving mode on a per-port basis. A port automatically enters power saving mode 10 seconds after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its TXOP/TXON pins and continues to monitor the RXIP/RXIN pins to detect incoming signals, which might be the 100Base-TX MLT-3 idle pattern, 10Base-T link pulses, or Auto-Negotiation’s FLP (Fast Link Pulse). After it detects any incoming signals, it wakes up from power saving mode and operates in normal mode according to the result of the connection.

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RTL8305SC Datasheet 8.2.13. Reg0.11 Power-Down Mode

The RTL8305SC implements power-down mode on a per-port basis. Setting MII Reg.0.11 forces the corresponding port of the RTL8305SC to enter power-down mode. This disables all transmit/receive functions, except SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface).

8.2.14. Crossover Detection and Auto Correction

During the link setup phase, the RTL8305SC checks whether it receives active signals on every port in order to determine if a connection can be established. In cases where the receiver data pin pair is connected to the transmitter data pin pair of the peer device and vice versa, the RTL8305SC automatically changes its configuration and swaps receiver/transmitter data pins as required. If a port is connected to a PC or NIC with MDI-X interface with a crossover cable, the RTL8305SC will reconfigure the port to ensure proper connection. This replaces the DIP switch commonly used for reconfiguring a port on a hub or switch.

By pulling-up EN_AUTOXOVER, the RTL8305SC identifies the type of connected cable and sets the port to MDI or MDIX. When switching to MDI mode, the RTL8305SC uses TXOP/N as transmit pairs; when switching to MDIX mode, the RTL8305SC uses RXIP/N as transmit pairs. This function is port-based. Pulling-down EN_AUTOXOVER disables this function, the RTL8305SC operates in MDI mode, in which TXOP/N represents transmit pairs, and RXIP/N represents receive pairs.

IEEE 802.3 compliant forced mode 100M ports with Autoxover have link issues with NWay (Auto-Negotiation) ports. It is recommended to not use Autoxover for forced 100M.

8.2.15. Polarity Detection and Correction

For better noise immunity and lower interference to ambient devices, the Ethernet electrical signal on a twisted pair cable is transmitted in differential form. That is, the signal is transmitted on two wires in each direction with inverse polarities (+/-). If wiring on the connector is faulty or a faulty transformer is used, the two inputs to a transceiver may carry signals with opposite but incorrect polarities. As a direct consequence, the transceiver will not work properly.

When the RTL8305SC operates in 10Base-T mode, it automatically reverses the polarity of its two receiver input pins if it detects that the polarities of the incoming signals on the pins is incorrect. However, this feature is unnecessary when the RTL8305SC is operating in 100Base-TX mode.

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RTL8305SC Datasheet 8.3. Advanced Functional Overview 8.3.1. Reset

The whole or just part of the RTL8305SC is initialized depending on the reset type. There are several ways to reset the RTL8305SC: hardware reset for the whole chip by pin RESET#, soft reset for all except PHY by register SoftReset, and PHY software reset for each PHY by register reset.

Hardware Reset: Pin RESET#=0 set to RESET#=1 (for at least 1ms). The RTL8305SC resets the whole chip and then gets initial values from pins and serial EEPROM.

Soft Reset: Write bit12 of Reg16 of PHY0 as 1. The RTL8305SC resets all except PHY and does not load EEPROM and Pin Registers with serial EEPROM and Pins. The SoftReset, EEPROM, and Pin registers are designed to provide a convenient way for users who want to use SMI to change the configuration. After changing the EEPROM or Pin registers via SMI (Serial Management Interface), the external device has to perform a soft reset in order to update the configuration.

PHY Software Reset: Write bit15 of Reg0 of a PHY as 1. The RTL8305SC will then reset this PHY.

Hardware Reset

Strap pinupon resetLoad EEPROMupon reset

Soft Reset: After loading EEPROM completely,the user may access EEPROM/Pin registers viaSMI. A Soft Reset to reset all except PHY is

required to update pin/EEPROM configuration.

Figure 10. Reset

Some setting values for operation modes are latched from those corresponding mode pins upon hardware reset. ‘Upon reset’ is defined as a short time after the end of a hardware reset. Other advanced configuration parameters may be latched from serial EEPROM if pin EnEEPROM=1.

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RTL8305SC Datasheet 8.3.2. Setup and Configuration

The RTL8305SC can be configured easily and flexibly by hardware pins upon reset, optional serial EEPROM upon reset, and internal registers (including PHY registers for each port and MAC register for global) via SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface). There are three methods of configuration:

1. Only hardware pins for normal switch applications

2. Hardware pins and serial EEPROM for advanced switch applications

3. Hardware pins and internal registers via SMI for applications with processor Three types of pins, each with internal pull-high resistors, are used for configuration: 1. Input pins used for strapping upon reset (unused after reset)

2. Input/Output pins (MTXD[3:2]/PRXD[3:2]/P4IRTag[1:0], MTXD[1:0]/PRXD[1:0]/LEDMode[1:0])

used for strapping upon reset and used as output pins after reset 3. Input/Output pins (all LEDs) used for strapping upon reset and used as LED indicator pins after reset.

The LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color LED mode, whose polarity depends on Spd status Pins with default value=1 are internal pull-high and use I/O pads. They can be left floating to set input value as high, but should not be connected to GND without a pull-down resistor.

The serial EEPROM shares two pins, SCL_MDC and SDA_MDIO, with SMI, and is optional for advanced configuration. SCL_MDC and SDA_MDIO are tri-state during hardware reset (pin RESET#=0). The RTL8305SC will try to automatically find the serial EEPROM upon reset only if pin EnEEPROM=1. If the first byte of the serial EEPROM is not 0xFF (NoEEPROM bit of the first byte=0), the RTL8305SC will load all contents of the serial EEPROM into internal registers. Otherwise, the RTL8305SC will use the default internal values.

Internal registers can still be accessed after reset via SMI (pin SCL_MDC and SDA_MDIO). Serial EEPROM signals and SMI signals must not exist at the same time. In order to use the SMI to flexibly change configuration, internal registers include the contents of some pins and all serial EEPROM. These registers do not work in real time and a Soft Reset is necessary after changing the EEPROM or pin registers.

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RTL8305SC Datasheet 8.3.3. Serial EEPROM Example: 24LC02

The 24LC02 interface is a 2-wire serial EEPROM interface providing 2K bits of storage space. The 24LC02 must be 3.3V compatible.

8.3.3.1 24LC02 Device Operation

Clock and Data transitions: The SDA pin is normally pulled high with an external resistor. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below.

Start Condition: A high-to-low transition of SDA with SCL high is the start condition and must precede any other command.

Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition.

Acknowledge: All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The 24LC02 sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.

Random Read: A random read requires a ‘dummy’ byte write sequence to load in the data word address. Sequential Read: For the RTL8305SC, the sequential reads are initiated by a random address read. After the 24LC02 receives a data word, it responds with an acknowledgement. As long as the 24LC02 receives an acknowledgement, it will continue to increment the data word address and clock out sequential data words in series.

SDASCLSTARTSTOP Figure 11. Start and Stop Definition

SCL189DATA INDATA OUTSTARTACKNOWLEDGE Figure 12. Output Acknowledge

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RTL8305SC Datasheet

Start

DeviceAddress

SDA

Data n

R/WACKACK

ACK

NO ACK

Write

WordAddress n

Start

DeviceAddress

Read

Stop

Dummy Write

Figure 13. Random Read

Read

DeviceAddress

SDA

Data n

R/W

ACK

ACK

Data n+1

ACK

Data n+x

NO ACK

ACK

ACK

Stop

Figure 14. Sequential Read

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RTL8305SC Datasheet 8.3.4. SMI

The SMI (Serial Management Interface) is also known as the MII Management Interface, and consists of two signals (MDIO and MDC). It allows external devices with SMI master mode (MDC is output) to control the state of the PHY and internal registers (SMI slave mode: MDC is input). MDC is an input clock for the RTL8305SC to latch MDIO on its rising edge. The clock can run from DC to 25MHz. MDIO is a bi-directional connection used to write data to, or read data from the RTL8305SC. The PHY address is from 0 to 4.

Table 145. SMI Read/Write Cycles

Preamble Start OP Code PHYAD REGAD Turn Around Data (32 bits) (2 bits) (2 bits) (5 bits) (5 bits) (2 bits) (16 bits)

Read 1……..1 01 10 A4A3A2A1A0 R4R3R2R1R0 Z0 D15…….D0 Write 1……..1 01 01 A4A3A2A1A0 R4R3R2R1R0 10 D15…….D0 Note: Z*: high-impedance. During idle time MDIO state is determined by an external 1.5KΩ pull-up resistor.

Idle Z* Z*

The RTL8305SC supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits. However, for the first cycle of MII management after power-on reset, a 32-bit preamble is needed.

To guarantee the first successful SMI transaction after power-on reset, the external device should delay at least 1second before issuing the first SMI Read/Write Cycle relative to the rising edge of reset.

8.3.5. Head-Of-Line Blocking

The RTL8305SC incorporates an advanced mechanism to prevent Head-Of-Line blocking problems when flow control is disabled. When the flow control function is disabled, the RTL8305SC first checks the destination address of the incoming packet. If the destination port is congested, the RTL8305SC will discard this packet to avoid blocking the next packet, which is going to a non-congested port.

8.3.6. Port-Based VLAN

If the VLAN function is enabled by pulling down the strapping pin DisVLAN, the default VLAN membership configuration by internal register is port 4 overlapped with all the other ports to form four individual VLANs. This default configuration of the input port could be modified via an attached serial EEPROM or SMI interface. The 16 VLAN membership registers designed into the RTL8305SC provide full flexibility for users to configure the input ports to associate with different VLAN groups. Each input port can join more than one VLAN group.

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RTL8305SC Datasheet Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to determine their VLAN association. All the packets received on a given input port will be forwarded to this port’s VLAN members. The RTL8305SC supports five VLAN indexes for each port to individually index this port to one of the 16 VLAN membership registers. These 16 VLAN membership registers, VLAN ID [A] membership bit [4:0] ~ VLAN ID [P] membership bit [4:0], describe which ports are the members of this VLAN. The RTL8305SC forwards packets to the members of this VLAN only (excluding the input port of this frame). A port that is not included in a VLAN’s member set cannot transmit packets to this VLAN.

Figure 15 illustrates a typical application. VLAN indexes and VLAN member definitions are set to form three different VLAN groups.

VLAN 1VLAN 2

P0P1P2P3P4Port 0 VLAN Index=0000Port 1 VLAN Index=0000Port 2 VLAN Index=0000Port 3 VLAN Index=0001Port 4 VLAN Index=0001Membership [A]0 0 1 1 1Membership [B]1 1 0 0 0Membership [C]0 0 0 0 0Membership [P]0 0 0 0 0RTL8305SC Figure 15. VLAN Grouping Example

For port-based VLAN configuration, each ingress port is allotted an index register to index to this port’s ‘Port VLAN Membership’ register, which can be defined in one of the registers from ‘VLAN ID [A] Membership bit [4:0]’ to ‘VLAN ID [P] Membership bit [4:0]’ register.

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RTL8305SC Datasheet Using the default value as an example:

• Port 0 VLAN Index[3:0]=2’b0000 means the member set of port 0 is defined in the ‘VLAN ID [A] Membership’ register • Port 1 VLAN Index[3:0]=2’b0001 means the member set of port 0 is defined in the ‘VLAN ID [B] Membership’ register • Port 2 VLAN Index[3:0]=2’b0010 means the member set of port 0 is defined in the ‘VLAN ID [C] Membership’ register • Port 3 VLAN Index[3:0]=2’b0011 means the member set of port 0 is defined in the ‘VLAN ID [A] Membership’ register • Port 4 VLAN Index[3:0]=2’b0100 means the member set of port 0 is defined in the ‘VLAN ID [A] Membership’ register

For non-VLAN tagged frames, the RTL8305SC performs port-based VLAN. It will use ‘Port n VLAN Index [3:0]’ register to index to a VLAN membership. The VLAN ID associated with this indexed VLAN membership is the Port VID (PVID) of this port.

8.3.7. IEEE 802.1Q Tagged-VID Based VLAN

The RTL8305SC supports 16 VLAN entries to perform 802.1Q tagged-VID based VLAN mapping. In 802.1Q VLAN mapping, the RTL8305SC uses a 12-bit explicit identifier in the VLAN tag to associate received packets with a VLAN. The 16 groups of VLAN membership registers, ‘VLAN ID [A] membership [4:0] ~ VLAN ID [P] membership [4:0]’, consist of the ports that are in the same VLAN corresponding to the registers defined in register ‘VLAN ID [A] [11:0] ~ VLAN ID [P] [11:0]’. If the VID of a VLAN-tagged frame does not hit any one of the registers in ‘VLAN ID [A] [11:0] ~ VLAN ID [P] [11:0]’, the RTL8305SC will perform port-based VLAN mapping to the member set indexed by register ‘Port n VLAN index [3:0]’. Otherwise, the RTL8305SC compares the explicit identifier in the VLAN tag with the 16 VLAN ID registers to determine the VLAN association of this packet, and then forwards this packet to the member set of this VLAN. Two VIDs are reserved for special purposes. One of them is all 1’s, which is reserved and currently unused. The other is all 0’s, which indicates a priority tag. A priority-tagged frame should be treated as an untagged frame.

When ‘802.1Q tag aware VLAN’ at PHY0 Reg.16.10 is enabled, the RTL8305SC performs 802.1Q tag-based VLAN mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q tag aware VLAN’ is disabled, the RTL8305SC performs only port-based VLAN mapping both on non-tagged and tagged frames. Figure 16 illustrates the processing flow when ‘802.1Q tag aware VLAN’ is disabled.

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RTL8305SC Datasheet Un-taggedTagged

------------Length/TypeLength/Type802.1QTagSADASADAP0P1P2P3P0VLANIndex=0000VID [A]=0x000VID [B]=0x001Membership [A]1 0 0 0 1Membership [B]1 0 0 1 0Membership [C]1 0 1 0 0SearchVIDTableVID [C]=0x002------------Length/TypeLength/Type802.1QTagSADAVID [P]=0x00fMembership [I]1 0 0 0 1P4SADARTL8305SC Figure 16. Tagged and Untagged Packet Forwarding when 802.1Q Tag Aware VLAN is Disabled

Two VLAN ingress filtering functions are supported by the RTL8305SC in registers. One is the ‘VLAN tag admit control’ defined in PHY0 Reg.16.8, which provides the ability to receive VLAN-tagged frames only. Untagged or priority tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’ defined in PHY0 Reg.16.9, which will drop frames if the receive port is not in the member set.

There are also two optional egress filtering functions supported by the RTL8305SC through strapping. One is ‘Leaky VLAN’ at PHY0 Reg18.11, which e . That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule. The other is ‘ARP VLAN’ at PHY0 Reg.18.10, which will broadcast ARP packets to all other ports, ignoring the egress rule.

8.3.8. Port VID (PVID)

In a router application, the router may want to know which input port this packet came from. The RTL8305SC supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on an egress packet. The VID information carried in the VLAN tag will be changed to a PVID. The RTL8305SC also provides an option to admit VLAN tagged packets with a specific PVID only. When this function is enabled, packets with an incorrect PVID, and non-tagged packets will be dropped.

The RTL8305SC uses an internal register, Port n VLAN index [3:0,] to index to one of the 16 VLAN entries. The VLAN ID associated with this indexed VLAN entry is the PVID for this port. Users may select VLAN insert/remove type 10 or 00 to insert a PVID on egress packets.

In 802.1Q tag-based VLAN applications, do not use a port-based VLAN PVID applications as the VID information carried in the VLAN tag will be replaced with a PVID.

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RTL8305SC Datasheet 8.3.9. Lookup Table Access

The RTL8305SC supports registers for the CPU to read or write an internal 1024-entry lookup table via the SMI interface. Before reading/writing from/to the internal forwarding table, the contents of internal register, Indirect Access Control [15:0] at PHY4 Register 16, should be filled correctly.

In the write cycle, the user must assign the write data in register Indirect Access Data 0, 1, 2, and 3 at PHY4 Register 17~20 first. Register 17, bits [1:0] along with bits [15:8] form a 10-bit field (Entry Index [9:0]), which is indirectly mapped to an entry in the lookup table. To execute write access, bit 0 in the Indirect Access Control register should be set to 0, and bit 1 should be set to 1. The CPU will poll bit 1 in Indirect Access Control to determine whether the write access is complete on not.

In the read cycle, the user only has to enter the read address of the lookup table in register Indirect Access Data 0, 1, 2, and 3 at PHY4 Register 17~20 first. Register 17, bits [1:0] along with bits [15:8] form a 10-bit field (Entry Index [9:0]). To execute read access, bit 0 in the Indirect Access Control register should be set to 1, and bit 1 should be set to 1 to trigger this command. The CPU will poll bit 1 in Indirect Access Control to determine whether read access is complete or not.

8.3.10. QoS Function

The RTL8305SC can recognize the QoS priority information of incoming packets to give a different egress service priority. The RTL8305SC identifies the packets as high priority based on several types of QoS priority information:

• Port-based priority

• 802.1p/Q VLAN priority tag

• TCP/IP’s TOS/DiffServ (DS) priority field

There are two priority queues; a high-priority queue, and a low-priority queue. The queue service rate is based on the Weighted Round Robin algorithm, the packet-based service weight ratio of the high-priority queue and low-priority queue can be set to 4:1, 8:1, 16:1 or ‘Always high priority first’ by hardware pins upon reset, or internal register via SMI after reset. Port-Based Priority

When port-based priority is applied, packets received from the high-priority port are sent to the high-priority queue of the destination port. High priority ports can be partially set by hardware pins, and wholly configured by registers.

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RTL8305SC Datasheet 802.1p-Based Priority

When 802.1p VLAN tag priority is enabled, the RTL8305SC recognizes the 802.1Q VLAN tag frames and extracts the 3-bit User Priority information from the VLAN tag. The RTL8305SC default sets the threshold of User Priority as 4. Therefore, VLAN tagged frames with User Priority value = 4~7 will be treated as high priority frames, and User Priority values=0~3 will be treated as low priority frames (follows the IEEE 802.1p standard). The threshold value can be modified in internal registers via an SMI interface or configured in EEPROM. DiffServ-Based Priority

When TCP/IP’s TOS/DiffServ(DS) based priority is enabled, the RTL8305SC recognizes TCP/IP Differentiated Services Codepoint (DSCP) priority information from the DS-field defined in RFC 2474. The DS field byte in IPv4 is a Type-of-Service (TOS) octet. The recommended DiffServ Codepoint is defined in RFC 2597 to classify the traffic into different service classes. The RTL8305SC extracts the codepoint value of DS-fields from IPv4 packets, and identifies the priority of the incoming IP packet according to the following definition:

High priority: Where the DS-field = (EF, Expected Forwarding:) 101110 or (AF, Assured Forwarding:) 001010; 010010; 011010; 100010 or (Network Control:) 110000 and 111000. Low priority: Where the DS-field = Other values.

The VLAN-tagged frame and 6-bit DS-field in the IPv4 frame format are shown below:

Table 146. 802.1Q VLAN Tag Frame Format

6 bytes 6 bytes 2 bytes 3 bits

DA SA 81-00 User-Priority

(0~3: Low-pri; 4~7: High-pri)

Table 147. IPv4 Frame Format

6 bytes 6 bytes 4 bytes DA SA 802.1Q Tag

(optional)

2 bytes 08-00

4 bits Version IPv4=

0100

4 bits IHL

6 bits TOS[0:5]= DS-field

---- ----

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RTL8305SC Datasheet 8.3.11. Insert/Remove VLAN Tag

The RTL8305SC supports four types of insert/remove VLAN packet tags, controlled by internal registers on a per-port basis. They are classified as follows: Type 11: Do not change packets (Default).

Type 10: Insert input port’s VLAN tags for non-tagged packets. Do not change packets if they are already tagged.

Type 01: Remove VLAN tags from tagged packets. Do not change packets if they are not tagged. Type 00: Remove VLAN tags from tagged packets, then insert the input port’s VLAN tags. For non-tagged packets, insert the input port’s VLAN tags.

If a tagged frame is less than 64 bytes after removal of the tag, it will be padded with an 0x20 pattern before the packet’s CRC field to fit the 64-byte minimum packet length of the IEEE 802.3 spec. The RTL8305SC will recalculate the FCS (Frame Check Sequence) if the frame has been changed.

8.3.12. Filtering/Forwarding Reserved Control Frame

The RTL8305SC supports the ability to forward or drop the frames of the IEEE 802.1D specified reserved multicast addresses.

Table 148. Reserved Multicast Address

Address Function Control Bit Control Bit=0 Control Bit=1

01-80-C2-00-00-00 Bridge Group Address N/A Broadcast 01-80-C2-00-00-01 Pause Control Frame N/A Drop 01-80-C2-00-00-03 IEEE802.1X Control FrameN/A Broadcast 01-80-C2-00-00-02 and Reserved EnForward Drop *Broadcast 01-80-C2-00-00-04 to 01-80-C2-00-00-0F

Any other multicast Address - N/A Broadcast Note: * Indicates the default setting.

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RTL8305SC Datasheet 8.3.13. Broadcast Storm Control

According to the latched value of the DISBRDCTRL pin upon reset, the RTL8305SC determines whether or not to proceed with broadcast storm control. Once enabled (DISBRDCTRL=0), after 64 consecutive broadcast packets (DID=FF-FF-FF-FF-FF-FF) are received by a particular port, this port will discard following incoming broadcast packets for approximately 800ms. Any non-broadcast packet can reset the time window and broadcast counter such that the scheme restarts.

Note: Trigger condition: consecutive 64 DID = FF-FF-FF-FF-FF-FF packets. Release condition: receive non-broadcast packet on or after 800ms.

8.3.14. Broadcast In/Out Drop

If some destination ports are blocking and the buffer is full, broadcast frames are dropped according to configuration.

1. Input Drop: Do not forward to any port and drop the frame directly

2. Output Drop: Forward only to non-blocking ports (Broadcast becomes multicast)

1. Broadcast packet from Port0

2. Buffer of Port4 is full, others are not full

Port 0 1 2 3 4

Full

Rx:

Port 0 1 2 3 4

Full

Rx:Input Drop

Output Drop

Figure 17. Input Drop vs. Output Drop

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RTL8305SC Datasheet 8.3.15. Loop Detection

Loops should be avoided between switch applications. The simplest loop as shown below results in: 1) Unicast frame duplication; 2) Broadcast frame multiplication; 3) Address table non-convergence. Frames may be transmitted from Switch1 to Switch 2 via Link 1, then returned to Switch 1 via Link 2.

Switch 1Switch 2Link 1Link 2

Figure 18. Loop Example

When the loop detection function is enabled, the RTL8305SC periodically sends out a broadcast 64-byte packet every 3~5 minutes and automatically detects whether there is a network loop (or bridge loop). If a loop is detected, the LoopLED# will be ON (active low or high). The LED goes out when both RTL8305SC ports of the loop are unplugged. The Loop frame length is 64 bytes and its format is shown below.

Table 149. Loop Frame Format

FFFF FFFF FFFF

SID

8899 0300 000…0000 CRC In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If the EEPROM is not used, a unique SID should be assigned via SMI after reset, and the default SID (52-54-4c-83-05-c0) should not be used.

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RTL8305SC Datasheet 8.3.16. MAC Local Loopback Return to External

Each port supports loopback of the MAC (return to external device) for diagnostic purposes.

Example 1: If the internal register, PHY4 Reg.22.13=0 (Local loopback), the RTL8305SC will forward local and broadcast packets from the input of Port 4 to the output of Port 4, and drop unicast packets from the input of Port 4. Other ports can still forward broadcast or unicast packets to Port 4.

Example 2: If the internal register, PHY3 Reg.22.13=0 (Local loopback), the RTL8305SC will “forward local and broadcast packets from the input of Port3 to the output of Port3” and “drop unicast packets from the input of Port3”. Other ports can still forward broadcast or unicast packets to port3.

This is especially useful for router applications performing mass production tests. This function is independent of PHY type (GxMode/GyMode/P4Mode[1:0]) and can be done on each mode. Below are two examples: In Example 1 the external device (CPU) is connected to the MII or SNI interface of Port 4. In Example 2, the external device (CPU) does not have an MII or SNI interface, so it uses the PCI interface to connect an RTL8139 to the UTP port of Port 4.

Example 1: LoopBack in External PHY Mode

RTL8305SCMII/SNICPUExample 2: LoopBack in UTP Mode

RTL8305SCUTPRTL8139PCICPU Figure 19. Port 4 Loopback

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RTL8305SC Datasheet 8.3.17. Reg.0.14 PHY Digital Loopback Return to Internal

The digital loopback mode of the PHY (return to internal MAC) may be enabled on a per-port basis by setting MII Reg.0.14 to 1. In digital loopback mode, the TXD of PHY is transferred directly to the RXD of PHY with TXEN changed to CRS_DV, and returns to MAC via an internal MII. The data stream coming from the MAC will not egress to the physical medium, and an incoming data stream from the network medium will be blocked in this mode. The packets will be looped back in 10Mbps full duplex or 100Mbps full duplex mode. This function is especially useful for diagnostic purposes. For example, a NIC can be used to send broadcast frames into port0 of the RTL8305SC and set Port1 to Reg0.14 Loopback. The frame will be looped back to port 0, so the received packet count can be checked to verify that the switch device is good. In this example, port0 can be 10M or 100M and full or half duplex.

MACInternal MIIPHY Figure 20. Reg. 0.14 Loopback

As the RTL8305SC only supports digital loopback in full duplex mode, PHY Reg.0.8 for each port will always be kept on 1 when digital loopback is enabled. The digital loopback only functions on broadcast packets (DA=FF-FF-FF-FF-FF-FF). In loopback mode, the link LED of the loopback port should always be ON, and the Speed and Duplex LED combined to reflect the link status (100full/10full) correctly, regardless of what the previous status of this loopback port was.

Consider a case where a port is initially unlinked. When we set this port to digital loopback mode, the RTL8305SC can get this port linked up within 100ms at the configured speed, and will block the sending of UTP or Fiber signals from this port.

8.3.18. LEDs

The RTL8305SC supports four parallel LEDs for each port, and two special LEDs (SELMIIMAC# and LOOPLED#). Each port has four LED indicator pins. Each pin may have different indicator meanings set by pins LEDMode[1:0]. Refer to the pin descriptions for details (Port LED Pins, on page 20). Upon reset, the RTL8305SC supports chip diagnostics and LED functions by blinking all LEDs once for 320ms. This function can be disabled by asserting EN_RST_LINK to 0. LED_BLINK_TIME determines the LED blinking period for activity and collision (1=43ms and 0=120ms). The parallel LEDs corresponding to

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RTL8305SC Datasheet port 4 can be tri-stated (disable LED functions) for MII port application by setting ENP4LED in EEPROM to 0. In UTP applications, this bit should be set to 1.

All LED pins are dual function pins: input operation for configuration upon reset, and output operation for LED after reset. If the pin input is floating upon reset, the pin output is active low after reset. Otherwise, if the pin input is pulled down upon reset, the pin output is active high after reset. Exception: Bi-color Link/Act mode of pin LED_ADD[4:0] when LEDMode[1:0]=10. Below is an example circuit for LEDs. The typical values for pull-down resistors are 10KΩ.

Floating

3.3V

330 ohm

RTL8305SCPull DownLED Pin330 ohm10K ohmRTL8305SCLED Pin

Figure 21. Floating and Pull-Down of LED Pins

For two-pin Bi-color LED mode (LEDMode[1:0]=10), Bi-color Link/Act (pin LED_ADD) and Spd (pin LED_SPD) can be used for one Bi-color LED package, which is a single LED package with two LEDs connected in parallel with opposite polarity. When LEDMode[1:0]=10, the active status of LED_ADD is the opposite of LED_SPD.

Table 150. Spd and Bi-Color Link/Act Truth Table

Spd: Input=Floating, Active Low. Spd: Input=Pull-down, Active High. Indication Bi-Color State Bi-color Link/Act: The active status Bi-color Link/Act: The active status of LED_ADD is the opposite of of LED_ADD is the opposite of

LED_SPD and does not interact with LED_SPD and does not interact with input upon reset. input upon reset.

Spd Link/Act Spd Link/Act

No Link Both Off 1 1 0 0 100M Link Green On 0 1 1 0 10M Link Yellow On 1 0 0 1 100M Act Green Flash 0 Flash 1 Flash 10M Act Yellow Flash 1 Flash 0 Flash

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RTL8305SC Datasheet

Yellow

LED_SPDLED_ADD

Figure 22. Two Pin Bi-color LED for SPD Floating or Pull-high

Green

Yellow

LED_ADDLED_SPD

Figure 23. Two Pin Bi-color LED for SPD Pull-down

Green

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RTL8305SC Datasheet 8.3.19. 1.8V Power Generation

The RTL8305SC can use a PNP transistor to generate 1.8V from a 3.3V power supply. This 1.8V is used for the digital core and analog receiver circuits. Do not use one PNP transistor for more than one RTL8305SC chip, even if the rating is enough. Use one transistor for each RTL8305SC chip.

Do not connect an inductor (bead) directly between the collector of the PNP transistor and AVDD18. This will adversely affect the stability of the 1.8V power to a significant degree.

3.3VBeadHVDD33DVDD33HVDD33, DVDD33: 3.3V2SB1188Ic(max.) = 2A1N4001Diode

1.8V47uF/10uF/0.1uFBead

Figure 24. Using a PNP Transistor to Transform 3.3V Into 1.8V

0 ΩRTL8305SCVCTRLAVDD18DVDD18DVDD18, AVDD18: 1.8V

Table 151. An Example Using Power Transistor 2SB1188

Symbol Limits Unit VCBO -40 V VCEO -32 V VEBO -5 V IC -2 A(DC) PC 0.5 W Tj 150 °C Tstg -55~+150 °C

Note: Absolute maximum ratings (Ta=25°C).

For more information, refer to http://www.rohm.com Parameter

Collector-base voltage Collector-emitter voltage Emitter-base voltage Collector current

Collector power dissipation Junction temperature Storage temperature

8.3.20. Crystal/Oscillator

The frequency is 25Mhz. The maximum Frequency Tolerance is +/-50ppm. The maximum Jitter is 150ps Peak-to-Peak.

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RTL8305SC Datasheet 9. Characteristics

9.1. Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified.

Table 152. Electrical Characteristics/Ratings

Parameter

Vcc Supply Referenced to GND Digital Input Voltage DC Output Voltage

Min -0.5 -0.5 -0.5

Max +4.0 VDD VDD

Units V V V

9.2. Operating Range Parameter

Storage Temperature

Ambient Operating Temperature (Ta)

3.3V Vcc Supply Voltage Range (HVDD33, DVDD33)

1.8V Vcc Supply Voltage Range (DVDD18, AVDD18)

Min Max Units -55 +150 °C 0 +70 °C

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RTL8305SC Datasheet 9.3. DC Characteristics Parameter

Power Supply Current for 1.8V

SYM Condition Icc 10Base-T, idle

10Base-T, Peak continuous 100% utilization 100Base-TX, idle

100Base-TX, Peak continuous 100% utilization Power saving Power down Icc 10Base-T, idle

10Base-T, Peak continuous 100% utilization 100Base-TX, idle

100Base-TX, Peak continuous 100% utilization Power saving Power down PS 10Base-T, idle

10Base-T, Peak continuous 100% utilization 100Base-TX, idle

100Base-TX, Peak continuous 100% utilization Power saving Power down Vih Vil Iin Cin Voh Vol |IOZ|

Min 40 500 460 470 40 40 110 100 110 100 60 60 295 1230 1191 1176 270 270 2.0 -10 2.25

Typical 45 525 470 480 45 45 120 110 120 110 65 65 477 1308 1242 1227 295.5 295.5

3

Max 50 550 480 490 50 50 130 120 130 120 70 70 519 1386 1293 1278 321 321 0.8 10 0.4 10

Units mA

Power Supply Current for 3.3V

mA

Total Power

Consumption for all Ports

mW

TTL Input High Voltage TTL Input Low Voltage TTL Input Current TTL Input Capacitance Output High Voltage Output Low Voltage Output Three State Leakage Current

V V uA pF V V uA

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RTL8305SC Datasheet 9.4. AC Characteristics Parameter

Differential Output Voltage, Peak-to-Peak Differential Output Voltage Symmetry Differential Output Overshoot Rise/Fall Time

Rise/Fall Time Imbalance Duty Cycle Distortion Timing Jitter

TD Differential Output Impedance (return loss)

SYM Condition

Transmitter, 100Base-TX

VOD 50Ω from each output to Vcc, Best-fit over 14

bit times

VOS 50Ω from each output to Vcc, |Vp+|/ |Vp-| VOO tr ,tf

Percent of Vp+ or Vp- 10-90% of Vp+ or Vp-

Min 4.6

Typical 1.007 99.1 3.1 4.1 0.17 0.2 0.87

Max

Units V % % ns ns ns ns dB

|tr - tf|

Deviation from best-fit time-grid, 010101 … Sequence Idle pattern Return loss margin from 2Hz to 80MHz for

reference resistance of 100Ω. The margin is the minimum difference between the limit line and the return loss curve Return loss margin from 2Hz to 80MHz for

reference resistance of 100Ω. The margin is the minimum difference between the limit line and the return loss curve

Transmitter, 10Base-T

VOD 50Ω from each output to Vcc, all pattern Ecm

Period of time from start of TP_IDL to link pulses or period of time between link pulses Peak output current on TD short circuit for 10 seconds.

Terminate each end with 50Ω resistive load

dB below fundamental, 20 cycles of all ones data

TP_IDL width

RD Differential Output Impedance (return loss)

4.6 dB

Differential Output Voltage, Peak-to-Peak TP_IDL Silence Duration TD Short Circuit Fault Tolerance

TD Common-Mode Output Voltage

Transmitter Output Jitter Harmonic Content

2.36 10.48 24 43.2 6 28 256

V ms mA mV ns dB ns

Start-of-idle Pulse Width

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RTL8305SC Datasheet 9.5. Digital Timing Characteristics Table 153. LED Timing

Parameter LED On Time LED Off Time

SYM Condition

LED Timing

tLEDon While LED blinking tLEDoff While LED blinking

MRXC/PTXC,PHY2PTXC,MDCMin 43 43

Typical

Max 120 120

Unitsms ms

MRXD/PTXD[3: 0],PHY2PTXD[3: 0],MRXDV/PTXEN,PHY2PTXEN,MCOL, PHY2PCOL,MDIOTsTh Figure 25. Reception Data Timing of MII/SNI/SMI Interface

MTXC/PRXC,PHY2PRXC,MDCTcycMTXD/PRXD[3:0],PHY2PRXD[3:0],MTXEN/PRXDV,PHY2PRXDV,PCOL, PHY2PCOL,MDIOTosToh Figure 26. Transmission Data Timing of MII/SNI/SMI Interface

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RTL8305SC Datasheet Table 154. MII & SMI DC Timing

Parameter

SYM Condition

MAC Mode MII Timing

100BaseT MTXC/MRXC, Tcyc MTXC/MRXC, MRXC/PTXC clock cycle MRXC/PTXC time

Tcyc MTXC/MRXC, MRXC/PTXC clock cycle 10BaseT MTXC/MRXC,

MRXC/PTXC time

Tos Output Setup time from MTXC/PRXC rising MTXD[3:0]/PRXD[3:0],

MTXEN/PRXDV Output edge to MTXD[3:0]/PRXD[3:0], Setup Time MTXEN/PRXDV

Toh Output Hold time from MTXC/PRXC rising MTXD[3:0]/PRXD[3:0],

MTXEN/PRXDV Output edge to MTXD[3:0]/PRXD[3:0], Hold Time MTXEN/PRXDV

Ts MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to MRXD[3:0]/PTXD[3:0],

MRXDV/PTXEN, MRXC/PTXC rising edge setup time MCOL/PCOL Setup Time

Th MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to MRXD/PTXD,

MRXDV/PTXEN, MRXC/PTXC rising edge hold time MCOL/PCOL Hold Time

PHY Mode MII Timing

100BaseT MTXC/MRXC, Tcyc MTXC/MRXC, MRXC/PTXC, PHY2PTXC, MRXC/PTXC, PHY2PRXC clock cycle time PHY2PTXC, PHY2PRXC

Tcyc MTXC/MRXC, MRXC/PTXC, PHY2PTXC, 10BaseT MTXC/PRXC,

MRXC/PTXC, PHY2PRXC clock cycle time PHY2PTXC, PHY2PRXC

Tos Output Setup time from MTXC/PRXC rising MTXD/PRXD[3:0],

PHY2PRXD[3:0], edge to MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV, PHY2PRXD[3:0], MTXEN/PRXDV, PHY2PRXDV PHY2PRXDV MCOL/PCOL, PHY2PCOL MCOL/PCOL,

PHY2PCOL Output Setup Time

Toh Output Hold time from MTXC/PRXC rising MTXD/PRXD[3:0],

PHY2PRXD[3:0], edge to MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV, PHY2PRXD[3:0], MTXEN/PRXDV, PHY2PRXDV PHY2PRXDV MCOL/PCOL, PHY2PCOL MCOL/PCOL,

PHY2PCOL Output Hold Time

Ts MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to MRXD/PTXD[3:0],

PHY2PTXD[3:0], MRXC/PTXC rising edge setup time MRXDV/PTXEN,

PHY2PTXEN Setup Time

Th MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to MRXD/PTXD[3:0],

PHY2PTXD[3:0], MRXC/PTXC rising edge hold time MRXDV/PTXEN,

PHY2PTXEN Hold Time

I/O Min Type MaxI I O

40±50

ppm

400±50

ppm 34 34.8 36

Units ns ns ns

O 4 5.2 6 ns

I 4 ns

I 2 ns

O

40±50

ppm 400±50 ppm

ns

O ns

O 17.2 18.2 19.2 ns

O 20.8 21.8 22.8 ns

I 4 ns

I 2 ns

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RTL8305SC Datasheet Parameter

MTXC/MRXC, MRXC/PTXC MTXD/PRXD[0], MTXEN/PRXDV, MCOL/PCOL Output Setup Time

MTXD/PRXD[0], MTXEN/PRXDV, MCOL/PCOL Output Hold Time

MRXD/PTXD[0],

MRXDV/PTXEN Setup Time

MTXD/PRXD[0], MTXEN/PRXDV,

MCOL/PCOL Hold Time MDC

MDIO Setup Time MDIO Hold Time MDIO Output Delay

Relative to Rising Edge of MDC

SYM Condition Tcyc Tos

PHY Mode SNI Timing

MTXC/PRXC, MRXC/PTXC clock cycle time

Output Setup time from MTXC/PRXC rising edge to MTXD[0]/PRXD[0], MTXEN/PRXDV, MCOL/PCOL

Output Hold time from MTXC/PRXC rising edge to MTXD[0]/PRXD[0], MTXEN/PRXDV, MCOL/PCOL MRXD[0]/PTXD[0], MRXDV/PTXEN to MRXC/PTXC rising edge setup time MTXD[0]/PRXD[0], MRXDV/PTXEN to MRXC/PTXC rising edge hold time SMI Timing

MDC clock cycle Write cycle Write cycle Read cycle

I/O Min Type MaxO O

100±50 ppm 36 38 40

Units ns ns

Toh O 59 60 61 ns

Ts I 4 ns

Th I 2 ns

Tcyc

Ts Th Tov I I I O 40 10 10 10 ns ns ns µs

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RTL8305SC Datasheet 9.6. Thermal Characteristics 9.6.1. Package Description

Table 155. Package Description

Item Parameter

Type QFP128 Device RTL8305SC Dimension (L x W) 14 x 20 mm Thickness 2.85 mm

9.6.2. PCB Description

Table 156. PCB Description

Item

Dimension (L x W) Number of Cu Layer

Parameter 50 x 70 mm

2 layers (80% of Cu trace coverage of top/bottom layer)

9.6.3. Assembly Material

Table 157. Assembly Material

Item Material Thermal Conductivity K (w/m-k)

Die Silicon 147 Lead Frame C7025 168 Silver Paste AG03*7 2.0 Mold Compound 6300HG 0.63 PCB

FR4 0.21 Cu 393

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RTL8305SC Datasheet 9.6.4. Simulation Analysis Conditions

Table 158. Simulation Analysis Conditions

Item

Air Flow Rate Control Condition Ambient Temperature

Parameter 0, 1, 2, 3 m/s Power=1.386 W 60°C

9.6.5. Results

Table 159. Results

Air Flow (m/s)

Tj (°C) Tc (°C) θJA (°C/W) ψJT (°C/W)

0 1 2 3

117.3 112.1 109.6 108.2 111.0 104.7 101.8 100.2 41.3 37.6 35.8 34.8 4.51 5.33 5.61 5.79 Where:

Tj is the maximum junction temperature. Tc is the maximum case temperature.

θJA is the junction-to-ambient thermal resistance. θJC is the junction-to-case thermal resistance.

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RTL8305SC Datasheet 10. Application Information

10.1. UTP (10Base-T/100Base-TX) Application In reviewing this material, please be advised that the center-tap on the primary side of the transformer must be left floating and should not be connected to ground through capacitors.

Table 160. Transformer Vendors

Vendor Quad Single Pulse H1164 H1102 Magnetic 1 ML164 ML102

Two types of transformers are generally used for the RTL8305SC. One is a Quad (4 port) transformer

with one common pin on both sides for an internal connected central tap. Another is a Single (1 port) transformer with two pins on both sides for a separate central tap.

RXIPRXINTransformer50Ω1%50Ω1%0.1uFAGNDRJ-4512341:1RTL8305SCTXOP50Ω1%0.1uF50Ω1%AGND1.8V0.1uFAGND51:1678TXONIBREF1.96ΚΩ, 1%AGND75Ω 75Ω 75Ω 50pF/2KVChassis GNDFigure 27. UTP Application for Transformer with Connected Central Tap

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RTL8305SC Datasheet

Pulse H1102Transformer1.8V0.1uFAGNDRXIP50Ω1%50Ω1%RJ-4575Ω 1:112345RXINRTL8305SCTXOP50Ω1%50Ω1%1.8V0.1uF1:175Ω 678TXONAGNDIBREF1.96ΚΩ, 1%75Ω 75Ω AGND50pF/2KVChassis GNDFigure 28. UTP Application for Transformer with Separate Central Tap

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RTL8305SC Datasheet 10.2. 100Base-FX Application The following is an example of an RTL8305SC connecting to a 3.3V fiber transceiver application circuit with a SIEMENS V23809-C8-C10 (3.3V~5V fiber transceiver, 1*9 SC Duplex Multimode 1300 nm LED Fast Ethernet/FDDI/ATM Optical Transceiver Module).

Fiber_RX_3.3V82Ω100Base-FXFiber Transceiver1 GND_RX2 RD+RXIPRXINFiber_RX_3.3V82Ω130ΩAGND3 RD-130Ω4 SDAGNDFiber_RX_3VFiber_TX_3VRTL8305SC82Ω5 VCC_RX6 VCC_TX7 TD-TXONTXOP82Ω130Ω8 TD+9 GND_TXAGND130ΩChassis GNDAGND Figure 29. 100Base-FX with 3.3V Fiber Transceiver Application

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RTL8305SC Datasheet Figure 30 shows an example of an RTL8305SC connected to a 5V fiber transceiver application circuit with a SIEMENS V23809-C8-C10 (3.3V~5V fiber transceiver, 1*9 SC Duplex Multimode 1300nm LED Fast Ethernet/FDDI/ATM Optical Transceiver Module).

Fiber_RX_5V

82Ω82Ω100Base-FXFiber Transceiver1 GND_RXRXIPRXINFiber_TX_5V50Ω50Ω2 RD+3 RD-4 SDRTL8305SC100Ω100Ω82Ω82ΩFiber_RX_5VFiber_TX_5V5 VCC_RX6 VCC_TX7 TD-TXONTXOP130Ω130Ω8 TD+9 GND_TX250Ω250ΩChassis GND Figure 30. 100Base-FX with 5V Fiber Transceiver Application

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RTL8305SC Datasheet 11. Design and Layout Guide

In order to achieve maximum performance using the RTL8305SC, good design attention is required throughout the design and layout process. The following are some suggestions to implement a high performance system. General Guidelines

• Provide a good power source, minimizing noise from switching power supply circuits (<50mV). • Verify the ability of critical components, e.g. clock source and transformer, to meet application requirements. • • • •

Keep power and ground noise levels below 50mV.

Use bulk capacitors (4.7µF-10µF) between the power and ground planes.

Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes. Keep de-coupling capacitors as close as possible to the RTL8305SC chip.

Differential Signal Layout Guidelines

• Keep differential pairs as close as possible and route both traces as identically as possible. • Avoid vias and layer changes if possible.

• Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane. Clock Circuit

• If possible, surround the clock by ground trace to minimize high-frequency emissions. • Keep the crystal or oscillator as close to the RTL8305SC as possible. 1.8V Power

• Do not connect a bead directly between the collector of the PNP transistor and AVDD18. This will significantly affect the stability of the 1.8V power supply. • Use a bulk capacitor (4.7µF-10µF) between the collector of the PNP transistor and the ground plane. • Do not use one PNP transistor for more than one RTL8305SC chip, even if the rating is enough. Use one transistor for each RTL8305SC chip.

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RTL8305SC Datasheet Power Plane

• Divide the power plane into 1.8V digital, 3.3V digital, and 1.8V analog.

• Use 0.1µF decoupling capacitors and bulk capacitors between each power plane and the ground plane. • Power line connects from the source to the RTL8305SC pin should be at least 10 mil wide. Ground Plane

• Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board. • Place a moat (gap) between the system ground and chassis ground.

• Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.

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RTL8305SC Datasheet 12. Mechanical Dimensions

See the Mechanical Dimensions notes on the next page.

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

SEATINGPLANESEE DETAIL “F”SEE DETAIL “A”DETAIL “F”DETAIL “A”GAGE PLANEBASEMETALWITHPLATING

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RTL8305SC Datasheet 12.1. Mechanical Dimensions Notes

Symbol Dimensions in inches Dimensions in mm Notes:

Min Typical Max Min TypicalMax 1. Dimensions D & E do not include interlead flash. A - - 0.134 - - 3.40 2. Dimension b does not include dambar rotrusion/intrusion. A1 0.004 0.010 0.036 0.10 0.25 0.91 3. Controlling dimension: Millimeter A2 0.102 0.112 0.122 2.60 2.85 3.10 4. General appearance spec. Should be based on final visual b 0.005 0.009 0.013 0.12 0.22 0.32 inspection. c 0.002 0.006 0.010 0.05 0.15 0.25 D 0.541 0.551 0.561 13.75 14.00 14.25 TITLE: PQFP-128 E 0.778 0.787 0.797 19.75 20.00 20.25 -CU L/F, FOOTPRINT 3.2 mm e 0.010 0.020 0.030 0.25 0.5 0.75 LEADFRAME MATERIAL: HD 0.665 0.677 0.689 16.90 17.20 17.50 APPROVE DOC. NO. HE 0.902 0.913 0.925 22.90 23.20 23.50 VERSION 1.2 L 0.027 0.035 0.043 0.68 0.88 1.08 PAGE L1 0.053 0.063 0.073 1.35 1.60 1.85 CHECK DWG NO. Q128 - 1 y - - 0.004 - - 0.10 DATE 12 February 2003 θ 0° - 12° 0° - 12° REALTEK SEMICONDUCTOR CORP.

13. Ordering Information

Table 161. Ordering Information

Part Number Package Status

RTL8305SC 128-pin PQFP RTL8305SC-LF 128-pin PQFP Lead (Pb)-Free package

Realtek Semiconductor Corp. Headquarters

No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw

5-port 10/100Mbps Single-Chip Dual MII Switch Controller

148 Track ID: JATR-1076-21 Rev. 1.2