DCP01B SERIESSBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004Miniature, 1W IsolatedUNREGULATED DC/DC CONVERTERSFEATURESDUp To 85% EfficiencyDThermal ProtectionDDevice-to-Device SynchronizationDShort-Circuit ProtectionDEN55022 Class B EMC PerformanceDUL1950 Recognized ComponentDJEDEC DIP-14 and SOP-14 PackagesAPPLICATIONSDPoint-of-Use Power ConversionDGround Loop EliminationDData AcquisitionDIndustrial Control and InstrumentationDTest EquipmentDESCRIPTIONThe DCP01B series is a family of 1W, unregulated,isolated DC/DC converters. Requiring a minimum ofexternal components and including on-chip deviceprotection, the DCP01B series provides extra featuressuch as output disable and synchronization of switchingfrequencies.The use of a highly-integrated package design results inhighly reliable products with a power density of 40W/in3(2.4W/cm3). This combination of features and small sizesmakes the DCP01B suitable for a wide range ofapplications.SYNCOUT800kHzOscillator÷2ResetPowerStageVOUT0VSYNCINWatch−dog/start−upPSUThermalShutdownIBIASVSPowerControllerIC0VPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Copyright 2000−2004, Texas Instruments Incorporatedwww.ti.com元器件交易网www.cecb2b.comDCP01B SERIES
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DCP01B SERIES5V modelsInput voltageStorage temperatureLead temperature (soldering, 10s)(1)SUPPLEMENTAL ORDERING INFORMATION
UNITVVV°C°CBasicModelNumber:1WProductVoltageInput:5VIn
VoltageOutput:5VOutDualOutput:ModelRevision:PackageCode:P=DIP−14
P−U=SOP−14(Gullwing)
DCP010505(D)(B)()
71829−40 to +125+27015V models24V modelsStresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periodsmay degrade device reliability. These are stress ratings only, andfunctional operation of the device at these or any other conditionsbeyond those specified is not implied.
ORDERING INFORMATION(1)
PRODUCTPACKAGE-LEADDIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)DIP-14SOP-14(4)PACKAGEDESIGNATORNVADUANVADUANVADUANVADUANVADUANVADUANVADUANVADUANVADUANVADUASPECIFIEDTEMPERATURERANGE−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°C−40°C to +100°CPACKAGEMARKINGDCP010505BPDCP010505BP−UDCP010512BPDCP010512BP−UDCP010515BPDCP010515BP−UDCP012405BPDCP012405BP−UDCP010505DBPDCP010505DBP−UDCP010512DBPDCP010512DBP−UDCP010515DBPDCP010515DBP−UDCP011512DBPDCP011512DBP−UDCP011515DBPDCP011515DBP−UDCP012415DBPDCP012415DBP−UORDERING NUMBER(2)DCP010505BPDCP010505BP−U/700DCP010512BPDCP010512BP−U/700DCP010515BPDCP010515BP−U/700DCP012405BPDCP012405BP−U/700DCP010505DBPDCP010505DBP−U/700DCP010512DBPDCP010512DBP−U/700DCP010515DBPDCP010515DBP−U/700DCP011512DBPDCP011512DBP−U/700DCP011515DBPDCP011515DBP−U/700DCP012415DBPDCP012415DBP−U/700TRANSPORTMEDIARailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelRailsTape and ReelSINGLE VOLTAGE(3)DCP010505DCP010512DCP010515DCP012405DUAL VOLTAGE(3)DCP010505DCP010512DCP010515DCP011512DCP011515DCP012415(1)
All devices also available in tray quatities. For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet,or refer to our web site at www.ti.com.
(2)Models with a (/) are available only in Tape and Reel in the quantities indicated (for example, /700 indicates 700 devices per reel). Ordering 700 pieces of
“DCP010505BP−U/700” will get a single 700-piece Tape and Reel.
(3)Single voltage versions have six active pins; dual voltage versions have seven active pins.(4)SOP package is gullwing surface-mount.
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted.
DCP01B SERIESPARAMETEROutputPowerRippleVoltage vs TemperatureInputVoltage range on VSIsolationVoltageLine RegulationVoltage Source (VS)Switching/SynchronizationOscillator frequency (fOSC)Sync input lowSync input currentDisable timeCapacitance loading on SYNCIN pinReliabilityDemonstratedThermal ShutdownIC temperature at shutdownShutdown currentTemperature RangeOperating(1)(2)
TEST CONDITIONS100% full loadO/P capacitor = 1µF, 50% loadRoom to coldRoom to hotMINTYP0.97200.0460.016MAXUNITSWmVPP%/°C%/°C−101s flash test60s test, UL1950(1)11+10%kVrmskVrms%changeof VSkHzMinimum VS ≤ IO constant ≤ typical VSTypical VS ≤ IO constant ≤ maximum VS115(2)Switcing frequency = fOSC/2VSYNC = +2VExternalMSL 3−(U) versions TA = +55°C−408000.47523+70+1503−40+100VµAµspF°C°CmA°CDuring UL1950 recognition tests only.
Line regulation is measured at constant load current. Line regulation = (VOUT at IOUT fixed)/VS. Variation % = VS min to VS typ, VS typ to VS max.
ELECTRICAL CHARACTERISTICS PER DEVICE
At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted.
INPUT VOLTAGE(V)VSPRODUCTDCP010505BDCP010505DBDCP010512BDCP010512DBDCP010515BDCP010515DBDCP011512DBDCP011515DBDCP012405BDCP012415DB(3)(4)
OUTPUT VOLTAGE(V)VNOM = VS Typical75% LOAD(3)LOAD REGULATION(%)10% TO 100% LOAD(4)NO LOADCURRENT(mA)IQ0% LOADTYP20222940344219201417EFFICIENCY(%)100% LOADTYP80818582828578807776BARRIERCAPACITANCE(pF)CISOVISO = 750VRMSTYP3.63.85.14.03.84.72.52.52.53.8MIN4.54.54.54.54.54.513.513.521.621.6TYP55555515152424MAX5.55.55.55.55.55.516.516.526.426.4MIN4.75±4.2511.4±11.414.25±14.25±11.4±14.254.75±14.25TYP5±512±1215±15±12±155±15MAX5.25±5.7512.6±12.615.75±15.75±12.6±15.755.25±15.75TYP19182119261911121310MAX31323837424139392335100% load current = 1W/VS typical.
Load regulation = (VOUT at 10% load − VOUT at 100% load)/VOUT at 75% load.
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PIN ASSIGNMENTS (Single Voltage Version)
NVA and DUA
PACKAGES(TOP VIEW)
PIN ASSIGNMENTS (Dual Voltage Version)
NVA and DUAPACKAGES(TOP VIEW)
VS0V
12
14SYNCINVS0V
12
14SYNCIN
DCP01B
0V+VOUT
NC
567
8
SYNCOUT
0V+VOUT−VOUT
567
DCP01DB
8
SYNCOUT
Terminal Functions (Single Voltage)
TERMINALNAMEVS0V0V+VOUTNCSYNCOUTSYNCINNO.12567814OII/OIIOODESCRIPTIONVoltage inputInput side commonOutput side common+Voltage outNot connectedUnrectified transformer outputSynchronization pinTerminal Functions (Dual Voltage)
TERMINALNAMEVS0V0V+VOUT−VOUTSYNCOUTSYNCINNO.12567814I/OIIOOOOIDESCRIPTIONVoltage inputInput side commonOutput side common+Voltage out−Voltage outUnrectified transformer outputSynchronization pinNOTE:I = input and O = output.NOTE:I = input and O = output.
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
At TA = 25°C, unless otherwise noted.
DCP010505B
OUTPUTRIPPLEvsLOAD(20MHzBW)
50454035Ripple(mVPP)VOUT(V)302520151050102030405060708090100Load(%)1µFCeramic4.7µFCeramic10µFCeramic5.55.45.35.25.15.04.94.84.74.64.54.44.54.64.7DCP010505BVOUTvsVS
4.84.95.0VS(V)5.15.25.35.45.5DCP010505BVOUTvsLOAD5.85.75.65.55.35.25.15.04.94.84.7
10
20
30
40
50
60
70
80
90
100
Load(%)
5510
20
Efficiency(%)5.4VOUT(V)757065608085DCP010505BEFFICIENCYvsLOAD30405060708090100
Load(%)
DCP010505DBVOUTvsLOAD
5.85.75.65.55.35.25.15.04.94.84.7
10
20
30
40
50
60
70
80
90
100
Load(%)
5510
20
Efficiency(%)5.4VOUT(V)75706560+VOUT−VOUT8580DCP010505DBEFFICIENCYvsLOAD
30405060708090100
Load(%)
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SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, unless otherwise noted.
DCP010512BVOUTvsLOAD
14.514.013.5
Efficiency(%)VOUT(V)13.012.512.011.511.0
10
20
30
40
50
60
70
80
90
100
Load(%)
90858075706560555010
20
DCP010512BEFFICIENCYvsLOAD
30405060708090100
Load(%)
DCP010512DBVOUTvsLOAD
14.514.013.5
Efficiency(%)13.0VOUT(V)12.512.011.511.010.510.0
10
20
30
40
50
60
70
80
90
100
Load(%)
+VOUT−VOUT555010
20
757065608580
DCP010512DBEFFICIENCYvsLOAD
30405060708090100
Load(%)
DCP010515BVOUTvsLOAD
18.017.517.0VOUT(V)16.516.015.515.014.514.0
10
20
30
40
50
60
70
80
90
100
Load(%)
Efficiency(%)858075706560555010
20
DCP010515BEFFICIENCYvsLOAD
30405060708090100
Load(%)
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, unless otherwise noted.
18
DCP010515DBVOUTvsLOAD
DCP010515DBEFFICIENCYvsLOAD
9085
17
Efficiency(%)+VOUT−VOUT1410
20
30
40
50
60
70
80
90
100
Load(%)
VOUT(V)8075706560555010
20
30
40
50
60
70
80
90
100
Load(%)
16
15
DCP012405BVOUTvsLOAD
5.605.505.40VOUT(V)5.305.205.105.004.904.80
10
20
30
40
50Load(%)
60
70
80
100
Efficiency(%)908070605040302010010
20
DCP012405BEFFICIENCYvsLOAD
30405060708090100
Load(%)
DCP010505B
CONDUCTEDEMISSIONS(125%Load)
60EmissionLevel,Peak(dBµA)EmissionLevel,Peak(dBµA)50403020100−10−20
0.15
1
Frequency(MHz)
10
30
6050403020100−10−20
0.15
DCP010505B
CONDUCTEDEMISSIONS(8%Load)
1
Frequency(MHz)
1030
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SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, unless otherwise noted.
DCP011512DBP
EFFICIENCYvsLOAD
+VOUT−VOUT80757065Efficiency(%)10203040506070809010060555045403510.50
Load(%)30102030405060708090100Load(%)DCP011512DBPVOUTvsLOAD
13.5013.0012.50VOUT(V)12.0011.5011.00
DCP011515DBPEFFICIENCYvsLOAD9080706050403010
20
30
40
50
60
70
80
90
100
Load(%)
17.0016.5016.00Efficiency(%)Efficiency(%)15.5015.0014.5014.0013.5013.0010
20
DCP011515DBPVOUTvsLOAD+VOUT−VOUT30405060708090100
Load(%)
DCP012415DBPEFFICIENCYvsLOAD
908070Efficiency(%)605040302010
20
30
40
50
60
70
80
90
100
Load(%)
VOUT(V)16.5016.0015.5015.0014.5014.0013.50
10
20
DCP012415DBPVOUTvsLOAD
+VOUT−VOUT30405060708090100
Load(%)
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
FUNCTIONAL DESCRIPTION
OVERVIEW
The DCP01B offers up to 1W of unregulated output powerwith a typical efficiency of up to 85%. This is achievedthrough highly integrated packaging technology and theimplementation of a custom power stage and control IC.The circuit design uses an advanced BiCMOS/DMOSprocess. For additional information, refer to the applicationnotes located in the DCP01B product folder at www.ti.com.
If synchronized devices are used, it should be noted thatat startup, all devices will draw maximum currentsimultaneously. This can cause the input voltage to dip. Ifit dips below the minimum input voltage (4.5V), the devicesmay not start up. A 2.2µF capacitor should be connectedclose to the input pins.
If more than eight devices are to be synchronized, it isrecommended that the SYNCIN pins are driven by anexternal device. Details are contained in ApplicationReport SBAA035, External Synchronization of theDCP01/02 Series of DC/DC Converters, available fordownload at www.ti.com.
POWER STAGE
This uses a push-pull, center-tapped topology switching at400kHz (divide-by-2 from 800kHz oscillator).
CONSTRUCTION
The DCP01B basic construction is the same as standardICs. There is no substrate within the molded package. TheDCP01B is constructed using an IC, rectifier diodes, anda wound magnetic toroid on a leadframe. Since there is nosolder within the package, the DCP01B does not requireany special PCB assembly processing. This results in anisolated DC/DC converter with inherently high reliability.
OSCILLATOR AND WATCHDOG
The onboard 800kHz oscillator generates the switchingfrequency via a divide-by-2 circuit. The oscillator can besynchronized to other DCP01B circuits or an externalsource, and is used to minimize system noise.
A watchdog circuit checks the operation of the oscillatorcircuit. The oscillator can be stopped by pulling the SYNCpin low. The output pins will be tri-stated. This will occur in2µs.
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCP01B can be disabled or enabled by driving theSYNC pin using an open drain CMOS gate. If the SYNCINpin is pulled low, the DCP01B will be disabled. The disabletime depends upon the external loading; the internaldisable function is implemented in 2µs. Removal of thepull-down will cause the DCP01B to be enabled.Capacitive loading on the SYNCIN pin should beminimized in order to prevent a reduction in the oscillatorfrequency.
THERMAL SHUTDOWN
The DCP01B is protected by a thermal shutdown circuit.If the on-chip temperature exceeds 150°C, the device willshut down. Once the temperature falls below 150°C,normal operation will resume. If the thermal conditioncontinues, operation will randomly cycle on and off. Thiswill continue until the temperature is reduced.
SYNCHRONIZATION
In the event that more than one DC/DC converter isneeded onboard, beat frequencies and other electricalinterference can be generated. This is due to the smallvariations in switching frequencies between the DC/DCconverters.
The DCP01B overcomes this by allowing devices to besynchronized to one another. Up to eight devices can besynchronized by connecting the SYNCIN pins together,taking care to minimize the stray capacitance. Straycapacitance (> 3pF) will have the effect of reducing theswitching frequency, or even stopping the oscillator circuit.
DECOUPLING
Ripple Reduction
A high switching frequency of 400kHz allows simplefiltering. To reduce ripple, it is recommended that at leasta 1µF capacitor is used on VOUT. Dual outputs should haveboth the positive and negative buses decoupled to VOUTground (pin 5). The required 2.2µF low equivalent seriesresistance (ESR) ceramic capacitor on the input of the 5Vto 15V versions, and the ≥ 0.47µF low-ESR ceramiccapacitor on the 24V versions help reduce ripple andnoise. See Application Bulletin SBVA012, DC-to-DCConverter Noise Reduction, available for download atwww.ti.com.
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Connecting the DCP01B in Series
Multiple DCP01B isolated 1W DC/DC converters can be
connected in series to provide nonstandard voltage rails.This is possible by using the floating outputs provided bythe DCP01B galvanic isolation.
Connect the positive VOUT from one DCP01B to thenegative VOUT (0V) of another, as shown in Figure 1. If theSYNCIN pins are tied together, the self-synchronizationfeature of the DCP01B will prevent beat frequencies on thevoltage rails. The SYNCIN feature of the DCP01B allowseasy connection in series, which reduces separate filteringcomponents.
The outputs on dual output DCP01B versions can also beconnected in series to provide two times the magnitude ofVOUT, as shown in Figure 2. For example, a dual 15VDCP01B could be connected to provide a 30V rail.
Connecting the DCP01B in Parallel
If the output power from one DCP01B is not sufficient, it ispossible to parallel the outputs of multiple DCP01Bconverters (see Figure 3). Again, the SYNCIN featureallows easy synchronization to prevent power-rail beatfrequencies at no additional filtering cost.
VSUPPLYCIN(1)VSSYNCIN0VDCP01BVOUT1COUT0VVOUT1+VOUT2VSCIN(1)SYNCIN0VCOMDCP01BVOUT2COUT0VNOTE:(1)CINrequiresalow−ESRceramiccapacitor:5Vto15Vversionis2.2µF;24Vversionisminimum0.47µF.COUT=1.0µF.Figure 1. Connecting the DCP01B in Series
VSUPPLYCIN(1)VSDCP0VCOM01B+VOUT−VOUT0VCOUT(1)COUT(1)+VOUT−VOUTNOTE:(1)CINrequiresalow−ESRceramiccapacitor:5Vto15Vversionis2.2µF;24Vversionisminimum0.47µF.COUT=1.0µF.Figure 2. Connecting Dual Outputs in Series
VSUPPLYCIN(1)VSSYNCIN0VDCP01BVOUTCOUT(1)0V2xPowerOutVSCIN(1)SYNCIN0VCOMDCP01BVOUTCOUT(1)0VNOTE:(1)CINrequiresalow−ESRceramiccapacitor:5Vto15Vversionis2.2µF;24Vversionisminimum0.47µF.COUT=1.0µF.Figure 3. Connecting Multiple DCP01Bs in Parallel
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
APPLICATION INFORMATION
The DCP01B, DCV01, and DCP02 are three families ofminiature DC/DC converters providing an isolatedunregulated voltage output. All are fabricated using aCMOS/DMOS process with the DCP01B replacing thefamiliar DCP01 family that was fabricated from a bipolarprocess. The DCP02 is essentially an extension of theDCP01B family providing a higher power output with asignificantly improved load regulation, and the DCV01 istested to a higher isolation voltage.
cycle so that all devices discharge together. A subsequentcharge cycle is only restarted when the last device hasfinished its discharge cycle.
OPTIMIZING PERFORMANCE
Optimum performance can only be achieved if the deviceis correctly supported. By the very nature of a switchingconverter, it requires power to be instantly available whenit switches on. If the converter has DMOS switchingtransistors, the fast edges will create a high currentdemand on the input supply. This transient load placed onthe input is supplied by the external input decouplingcapacitor, thus maintaining the input voltage. Therefore,the input supply does not see this transient (this is ananalogy to high-speed digital circuits). The positioning ofthe capacitor is critical and must be placed as close aspossible to the input pins and connected via alow-impedance path.
The optimum performance is primarily dependent on twofactors:
TRANSFORMER DRIVE CIRCUIT
Transformer drive transistors have a characteristically lowvalue of transistor on resistance (RDS); thus, more poweris transferred to the transformer. The transformer drivecircuit is limited by the base current available to switch onthe power transistors driving the transformer and theircharacteristic current gain (beta), resulting in a slowerturn-on time. Consequently, more power is dissipatedwithin the transistor. This results in a lower overallefficiency, particularly at higher output load currents.
1.Connection of the input and output circuits for
minimal loss.2.The ability of the decoupling capacitors to maintain
the input and output voltages at a constant level.PCB Design
The copper losses (resistance and inductance) can beminimized by the use of mutual ground and power planes(tracks) where possible. If that is not possible, use widetracks to reduce the losses. If several devices are beingpowered from a common power source, a star-connectedsystem for the track must be deployed; devices must notbe connected in series, as this will cascade the resistivelosses. The position of the decoupling capacitors isimportant. They must be as close to the devices aspossible in order to reduce losses. See the PCB Layoutsection for more details.
SELF-SYNCHRONIZATION
The input synchronizations facility (SYNCIN), allows foreasy synchronizing of multiple devices. If two to eightdevices (maximum) have their respective SYNCIN pinsconnected together, then all devices will be synchronized.Each device has its own onboard oscillator. This isgenerated by charging a capacitor from a constant currentand producing a ramp. When this ramp passes athreshold, an internal switch is activated that dischargesthe capacitor to a second threshold before the cycle isrepeated.
When several devices are connected together, all theinternal capacitors are charged simultaneously.
When one device passes its threshold during the chargecycle, it starts the discharge cycle. All the other devicessense this falling voltage and, likewise, initiate a discharge
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Decoupling Ceramic Capacitors
All capacitors have losses due to their internal equivalent
series resistance (ESR), and to a lesser degree theirequivalent series inductance (ESL). Values for ESL arenot always easy to obtain. However, some manufacturersprovide graphs of Frequency versus CapacitorImpedance. These will show the capacitors’ impedancefalling as frequency is increased (see Figure 4). As thefrequency is increased, the impedance will stopdecreasing and begin to rise. The point of minimumimpedance indicates the capacitors’ resonant frequency.This frequency is where the components of capacitanceand inductance reactance are of equal magnitude. Beyondthis point, the capacitor is not effective as a capacitor.
Input Capacitor and the effects of ESR
If the input decoupling capacitor is not ceramic with< 20mΩ ESR, then at the instant the power transistorsswitch on, the voltage at the input pins will fall momentarily.Should the voltage fall below approximately 4V, the DCPwill detect an under-voltage condition and switch the DCPdrive circuits to the off state. This is carried out as aprecaution against a genuine low input voltage conditionthat could slow down or even stop the internal circuits fromoperating correctly. This would result in the drivetransistors being turned on too long, causing saturation ofthe transformer and destruction of the device.
Following detection of a low input voltage condition, thedevice switches off the internal drive circuits until the inputvoltage returns to a safe value. Then the device tries torestart. If the input capacitor is still unable to maintain theinput voltage, shutdown recurs. This process is repeateduntil the capacitor is charged sufficiently to start the devicecorrectly. Otherwise, the device will be caught up in a loop.Normal startup should occur in approximately 1ms frompower being applied to the device. If a considerably longerstartup duration time is encountered, it is likely that either(or both) the input supply or the capacitors are notperforming adequately.
For 5V to 15V input devices, a 2.2µF low-ESR ceramiccapacitor will ensure a good startup performance, and forthe remaining input voltage ranges, 0.47µF ceramiccapacitors are good. Tantalum capacitors are notrecommended, since most do not have low-ESR valuesand will degrade performance. If tantalum capacitors mustbe used, close attention must be paid to both the ESR andvoltage as derated by the vendor.
ZXL0fOFrequencyWhere:XCisthereactanceduetothecapacitance,XListhereactanceduetotheESLfOtheresonantfrequencyZ=√(XC−XL)2+(ESR)2Figure 4. Capacitor Impedance vs Frequency
At fO, XC = XL; however, there is a 180° phase differenceresulting in cancellation of the imaginary component. Theresulting effect is that the impedance at the resonant pointis the real part of the complex impedance; namely, thevalue of the ESR. The resonant frequency must be wellabove the 800kHz switching frequency of the DCP andDCVs.
The effect of the ESR is to cause a voltage drop within thecapacitor. The value of this voltage drop is simply theproduct of the ESR and the transient load current, asshown in Equation (1):
Output Ripple Calculation Example
DCP020505: Output voltage 5V, Output current 0.4A. Atfull output power, the load resistor is 12.5Ω. Outputcapacitor of 1µF, ESR of 0.1Ω. Capacitor discharge time1% of 800kHz (ripple frequency):
tDIS = 0.0125µst = C × RLOAD
t = 1 × 10−6 × 12.5 = 12.5µsVDIS = VO(1 − EXP(−tDIS/τ))VDIS = 5mV
By contrast the voltage dropped due to the ESR:
VESR = ILOAD × ESRVESR = 40mV
Ripple voltage = 45mV
Clearly, increasing the capacitance will have a muchsmaller effect on the output ripple voltage than reducingthe value of the ESR for the filter capacitor.
VIN+VPK*(ESR ITR)
Where:
VIN is the voltage at the device input.
(1)
VPK is the maximum value of the voltage on thecapacitor during charge.ITR is the transient load current.
The other factor that affects the performance is the valueof the capacitance. However, for the input and the full waveoutputs (single-output voltage devices), the ESR is thedominant factor.
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
DUAL OUTPUT VOLTAGE DCP AND DCVs
The voltage output for the dual DCPs is half wave rectified;therefore, the discharge time is 1.25µs. Repeating theabove calculations using the 100% load resistance of 25Ω(0.2A per output), the results are shown below:
τ = 25µsTDIS = 1.25µs.VDIS = 244mVVESR = 20mV
Ripple Voltage = 266mV
This time, it is the capacitor discharging that is contributingto the largest component of ripple. Changing the outputfilter to 10µF, and repeating the calculations:
Ripple Voltage = 45mV.
This value is composed of almost equal components.The above calculations are given only as a guide.Capacitor parameters usually have large tolerances andcan be susceptible to environmental conditions.
The Sync pin, when not being used, is best left as a floatingpad. A ground ring or annulus connected around the pinwill prevent noise being conducted onto the pin. If the Syncpin is being connected to one or more Sync pins, then thelinking trace should be narrow and must be kept short inlength. In addition, no other trace should be in closeproximity to this trace because that will increase the straycapacitance on this pin, and that will effect theperformance of the oscillator.
Ripple and Noise
Careful consideration should be given to the layout of thePCB, in order that the best results can be obtained.The DCP01B is a switching power supply and as such canplace high peak current demands on the input supply. Inorder to avoid the supply falling momentarily during thefast switching pulses, ground and power planes should beused to connect the power to the input of DCP01B. If thisis not possible, then the supplies must be connected in astar formation with the traces made as wide as possible.If the SYNCIN pin is being used, then the trace connectionbetween device SYNCIN pins should be short to avoidstray capacitance. If the SYNCIN pin is not being used, itis advisable to place a guard ring (connected to inputground) around this pin to avoid any noise pick up.The output should be taken from the device using groundand power planes; this ensures minimum losses.A good quality low-ESR ceramic capacitor placed as closeas practical across the input will reduce reflected rippleand ensure a smooth startup.
A good quality low-ESR capacitor (ceramic preferred)placed as close as practical across the rectifier outputterminal and output ground gives the best ripple and noiseperformance. See SBVA012 for more information on noiserejection.
PCB LAYOUT
Figure 5 and Figure 6 illustrate a printed circuit board(PCB) layout for the two conventional (DCP01/02,DCV01), and two SO-28 surface-mount packages(DCP02U). Figure 7 shows the schematic.
Input power and ground planes have been used, providinga low-impedance path for the input power. For the output,the common or 0V has been connected via a ground plane,while the connections for the positive and negative voltageoutputs are conducted via wide traces in order to minimizelosses.
The location of the decoupling capacitors in closeproximity to their respective pins ensures low losses dueto the effects of stray inductance; thus, improving the rippleperformance. This is of particular importance to the inputdecoupling capacitor as this supplies the transient currentassociated with the fast switching waveforms of the powerdrive circuits.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisableto provide ground planes on the input and output.
13
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SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
Figure 5. Example of PCB Layout, Component-Side View
Figure 6. Example of PCB Layout, Non-component-Side View
14
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DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
CON1VS10V1+V1R1COM1R2−V1C5C4−1C47−V3C3C2−1C251C126DCP02xPCOM3R6C14C15SYNC14JP1VS30S3+V3R5C13C1212C1112313CON3SYNC282726DCP02xUNCJP114CON2VS20V2+V2R3COM2R4−V2C10C9−1C97−V4C8C7−1C75C6126DCP02xPCOM4R8C20C19SYNC14JP2VS40S4+V4R7C17C1812C1612313CON4SYNC282726NCDCP02xUJP214(1)(2)Capacitors C2−1, C4−1, C7−1, and C9−1 are through-hole plated components connected in parallel with C2, C4, C7 and C9 (1206 SMD), respectively.For optimum low-noise performance, use low-ESR capacitors.(3)Do not connect the SYNC pin jumper (JP1−JP4) if the SYNC function is not being used.(4)Connections to the power input should be made with a minimum wire of 16/0.2 twisted pair, with the length kept short.(5)VSx and 0Vx are input supply and ground respecively (x represents the channel).(6)+Vx and −Vx are the positive and negative outputs, referenced to a common ground COMx.(7)JPx are the links used for self-synchronization; if this facility is not being used, the links should be unconnected.(8)R1−R8 are the power output loads; do not fit these if an external load is connected.(9)CON1 and CON2 are DIL-14; CON3 and CON4 are SO-28 packages.(10)NC = not connected.Figure 7. Example of PCB Layout, Schematic Diagram
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PACKAGEOPTIONADDENDUM
www.ti.com
30-Mar-2005
PACKAGINGINFORMATION
OrderableDeviceDCP010505BPDCP010505BP-UDCP010505BP-U/700DCP010505DBPDCP010505DBP-UDCP010505DBP-U/700
DCP010512BPDCP010512BP-UDCP010512BP-U/700DCP010512DBPDCP010512DBP-UDCP010512DBP-U/700
DCP010515BPDCP010515BP-UDCP010515BP-U/700DCP010515DBPDCP010515DBP-UDCP010515DBP-U/700
DCP011512DBPDCP011512DBP-UDCP011512DBP-U/700
DCP011515DBPDCP011515DBP-UDCP011515DBP-U/700
DCP012415DBPDCP012415DBP-UDCP012415DBP-U/700
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypePDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOPPDIPSOPSOP
PackageDrawingNVADUADUANVADUADUANVADUADUANVADUADUANVADUADUANVADUADUANVADUADUANVADUADUANVADUADUA
PinsPackageEcoPlan(2)
Qty777777777777777777777777777
252570025257002525700252570025257002525700252570025257002525700
TBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBDTBD
Lead/BallFinish
CUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPBCUSNPB
MSLPeakTemp(3)Level-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HRLevel-NA-NA-NALevel-3-240C-168HRLevel-3-240C-168HR
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS)orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
Addendum-Page1
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PACKAGEOPTIONADDENDUM
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30-Mar-2005
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
Addendum-Page2
元器件交易网www.cecb2b.comMECHANICAL DATAMPDI058 – APRIL 2001NVA (R-PDIP-T7/14)DPLASTIC DUAL-IN-LINE0.775 (19,69)0.735 (18,67)1480.280 (7,11)0.240 (6,10)D17IndexAreaHBase Plane0.070 (1,78)0.045 (1,14)0.195 (4,95)0.115 (2,92)0.325 (8,26)0.300 (7,62)E0.015 (0,38)MINC– C –0.210 (5,33)MAXC0.005 (0,13)DMINFull Lead4 PL0.100 (2,54)Seating Plane0.022 (0,56)0.014 (0,36)0.010 (0,25)MC0.150 (3,81)0.115 (2,92)C0.300 (7,63)E0.014 (0,36)0.008 (0,20)0.060 (1,52)0.000 (0,00)F0.430 (10,92)MAXF4202489/A 03/01NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Dimensions are measured with the packageseated in JEDEC seating plane gauge GS-3.D.Dimensions do not include mold flash or protrusions.Mold flash or protrusions shall not exceed 0.010 (0,25).E.Dimensions measured with the leads constrained to beperpendicular to Datum C.F.Dimensions are measured at the lead tips with theleads unconstrained.G.Pointed or rounded lead tips are preferred to easeinsertion.H.Lead shoulder maximum dimension does not includedambar protrusions. Dambar protrusions shall not exceed0.010 (0,25).I.Distance between leads including dambar protrusionsto be 0.005 (0,13) minumum.J.A visual index feature must be located within thecross–hatched area.K.For automatic insertion, any raised irregularity on thetop surface (step, mesa, etc.) shall be symmetricalabout the lateral and longitudinal package centerlines.L.Falls within JEDEC MS-001-AA.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comMECHANICAL DATAMPDS097 – APRIL 2001DUA (R-PDSO-G7/14)PLASTIC SMALL-OUTLINEC0.775 (19,69)140.735 (18,67)80.280 (7,11)0.240 (6,10)CIndexArea10.022 (0,56)0.014 (0,36)70.420 (10,70)0.405 (10,30)0.070 (1,78)0.045 (1,14)D0.210 (5,33)MAX0.325 (8,26)0.300 (7,62)BasePlaneSeatingPlane0.043 (1,10)0.025 (0,65)0.057 (1,45)0.045 (1,15)0.014 (0,36)0.008 (0,20)0.100 (2,54)0.005 (0,13) MINFull Lead4 PLC0.015 (0,38)MIN0\"5°4202490/A 03/01NOTES:A.All linear dimensions are in inches (millimeters).B.This drawing is subject to change without notice.C.Dimensions do not include mold flash or protrusions.Mold flash or protrusions shall not exceed 0.010 (0,25).D.Lead shoulder maximum dimension does not includedambar protrusions. Dambar protrusions shall not exceed0.010 (0,25).E.Distance between leads including dambar protrusionsto be 0.005 (0,13) minimum.F.A visual index feature must be located within thecross–hatched area.G.For automatic insertion, any raised irregularity on the topsurface (step, mesa, etc.) shall be symmetrical aboutthe lateral and longitudinal package centerlines.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.com
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