元器件交易网www.cecb2b.comMOTOROLASEMICONDUCTOR TECHNICAL DATA8ĆBit Synchronous BinaryUp CounterThe MC10E/100E016 is a high-speed synchronous, presettable,cascadable 8-bit binary counter. Architecture and operation are the sameas the MC10H016 in the MECL 10H family, extended to 8-bits, as shownin the logic symbol.The counter features internal feedback of TC, gated by the TCLD(terminal count load) pin. When TCLD is LOW (or left open, in which caseit is pulled LOW by the internal pull-downs), the TC feedback is disabled,and counting proceeds continuously, with TC going LOW to indicate anall-one state. When TCLD is HIGH, the TC feedback causes the counterto automatically reload upon TC = LOW, thus functioning as aprogrammable counter. The Qn outputs do not need to be terminated forthe count function to operate properly. To minimize noise and power,unused Q outputs should be left unterminated.MC10E016MC100E0168-BIT SYNCHRONOUSBINARY UP COUNTER••••••••700MHz Min. Count Frequency1000ps CLK to Q, TCInternal TC Feedback (Gated)8-BitFully Synchronous Counting and TC GenerationAsynchronous Master ResetExtended 100E VEE Range of –4.2V to –5.46V75kΩ Input Pulldown ResistorsFUNCTION TABLEPinout: 28-Lead PLCC (Top View)PE25MRCLK26272812345P26P37P48VCCO9Q010Q111Q2CE24P723P622P521VCCO20TC1918171615141312Q7Q6VCCQ5VCCOQ4Q3CEXLLHXXPELHHHXXTCLDXLHXXXMRLLLLLHCLKZZZZZZXFunctionLoad Parallel (Pn to Qn)Continuous CountCount; Load Parallel on TC = LOWHoldMasters Respond, Slaves HoldReset (Qn : = LOW, TC : = HIGH)FN SUFFIXPLASTIC PACKAGECASE 776-02TCLDVEENCP0P1Z= clock pulse (low to high);ZZ= clock pulse (high to low)PIN NAMESPinP0–P7Q0–Q7CEPEMRCLKTCTCLDFunctionParallel Data (Preset) InputsData OutputsCount Enable Control InputParallel Load Enable Control InputMaster ResetClockTerminal Count OutputTC-Load Control Input* All VCC and VCCO pins are tied together on the die.12/93© Motorola, Inc. 19962–1REV 2元器件交易网www.cecb2b.comMC10E016 MC100E0168-BIT BINARY COUNTER LOGIC DIAGRAMQ0PETCLDQ1Q7Q0MCEBIT 0POP1MASTERSLAVEQ0CEBIT 1Q0MCEQQ10Q2Q3Q4Q5Q6P7BIT 7MRCLKBITS 2–65TCNote that this diagram is provided for understanding of logic operation only.It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.MOTOROLA2–2ECLinPS and ECLinPS LiteDL140 — Rev 4元器件交易网www.cecb2b.comMC10E016 MC100E016DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)0°CSymbolIIHIEECharacteristicInput HIGH CurrentPower Supply Current10E100E151151mintypmax150181181151151min25°Ctypmax150181181151174min85°Ctypmax150181208UnitµAmAConditionAC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)0°CSymbolfCOUNTtPLHtPHLCharacteristicMax. Count FrequencyPropagation Delay to OutputCLK to QMR to QCLK to TCMR to TCSetup TimePnCEPETCLDHold TimePnCEPETCLDReset Recovery TimeMinimum Pulse WidthCLK, MRRise/Fall Times20 - 80%min70060060055062515060060050035000100900400300510800typ900725775775775–30400400300100–400–400–300700100010009001000maxmin7006006005506251506006005003500010090040030051080025°Ctyp900725775775775–30400400300100–400–400–300700100010009001000maxmin70060060055062515060060050035000100900400ps30051085°Ctyp900725775775775–30400400300100–400–400–300700psps1000100010501000psmaxUnitMHzpsConditiontsthtRRtPWtrtfECLinPS and ECLinPS LiteDL140 — Rev 42–3MOTOROLA元器件交易网www.cecb2b.comMC10E016 MC100E016FUNCTION TABLEFunctionLoadCountPELHHHHLHHHHHHHHXCEXLLLLXHHLLLLLLXMRLLLLLLLLLLLLLLHTCLDXLLLLXXXHHHHHHXCLKZZZZZZZZZZZZZZXP7-P4HXXXXHXXHHHHHHXP3HXXXXHXXLLLLLLXP2HXXXXHXXHHHHHHXP1LXXXXLXXHHHHHHXP0LXXXXLXXLLLLLLXQ7-Q4HHHHLHHHHHHHHHLQ3HHHHLHHHHHHLLHLQ2HHHHLHHHHHHHHLLQ1LLHHLLLLLHHHHLLQ0LHLHLLLLHLHLHLLTCHHHLHHHHHHLHHHHLoadHoldLoad OnTerminalCountResetApplications InformationCascading Multiple E016 DevicesFor applications which call for larger than 8-bit countersmultiple E016s can be tied together to achieve very widebit width counters. The active low terminal count (TC)output and count enable input (CE) greatly facilitate thecascading of E016 devices. Two E016s can be cascadedwithout the need for external gating, however for counterswider than 16 bits external OR gates are necessary forcascade implementations.Figure 1 below pictorially illustrates the cascading of 4E016s to build a 32-bit high frequency counter. Note the E101gates used to OR the terminal count outputs of the lower orderE016s to control the counting operation of the higher orderbits. When the terminal count of the preceding device (ordevices) goes low (the counter reaches an all 1s state) themore significant E016 is set in its count mode and will countone binary digit upon the next positive clock transition. Inaddition, the preceding devices will also count one bit thussending their terminal count outputs back to a high stateLOADQ0 –> Q7Q0 –> Q7Q0 –> Q7CEE016PEQ0 –> Q7disabling the count operation of the more significant countersand placing them back into hold modes. Therefore, for anE016 in the chain to count, all of the lower order terminal countoutputs must be in the low state. The bit width of the countercan be increased or decreased by simply adding orsubtracting E016 devices from Figure 1 and maintaining thelogic pattern illustrated in the same figure.The maximum frequency of operation for the cascadedcounter chain is set by the propagation delay of the TC outputand the necessary setup time of the CE input and thepropagation delay through the OR gate controlling it (for 16-bitcounters the limitation is only the TC propagation delay andthe CE setup time). Figure 1 shows EL01 gates used to controlthe count enable inputs, however, if the frequency of operationis lower a slower, ECL OR gate can be used. Using the worstcase guarantees for these parameters from the ECLinPS databook, the maximum count frequency for a greater than 16-bitcounter is 500MHz and that for a 16-bit counter is 625MHz.LOCEE016LSBPECEE016PECEE016MSBPECLKP0 –> P7TCCLKP0 –> P7TCEL01CLKTCEL01CLKTCP0 –> P7P0 –> P7CLOCKFigure 1. 32-Bit Cascaded E016 CounterMOTOROLA2–4ECLinPS and ECLinPS LiteDL140 — Rev 4元器件交易网www.cecb2b.comMC10E016 MC100E016Applications Information (continued)Note that this assumes the trace delay between the TCoutputs and the CE inputs are negligible. If this is notthe case estimates of these delays need to be added tothe calculations.where:P0 = LSB and P7 = MSBForcing this input condition as per the setup in Figure 2 willresult in the waveforms of Figure 3. Note that the TC output isused as the divide output and the pulse duration is equal to aTable 1. Preset Values for Various Divide RatiosDivideRatio2345••112113114••2255256P7HHHH••HHH••LLLP6HHHH••LLL••LLLPreset Data InputsP5HHHH••LLL••LLLP4HHHH••HLL••LLLP3HHHH••LHH••LLLP2HHHL••LHH••LLLP1HLLH••LHH••HLLP0LHLH••LHL••LHLProgrammable DividerThe E016 has been designed with a control pin whichmakes it ideal for use as an 8-bit programmable divider. TheTCLD pin (load on terminal count) when asserted reloads thedata present at the parallel input pin (Pn’s) upon reachingterminal count (an all 1s state on the outputs). Because thisfeedback is built internal to the chip, the programmabledivision operation will run at very nearly the same frequencyas the maximum counting frequency of the device. Figure 2below illustrates the input conditions necessary for utilizing theE016 as a programmable divider set up to divide by 113.HP7HLHPECETCLDCLKQ7Q6Q5Q4Q3Q2Q1Q0TCLP6LP5LP4HP3HP2HP1HP0Figure 2. Mod 2 to 256 Programmable DividerTo determine what value to load into the device toaccomplish the desired division, the designer simply subtractsthe binary equivalent of the desired divide ratio from the binaryvalue for 256. As an example for a divide ratio of 113:Pn’s = 256 – 113 = 8F16 = 1000 1111full clock period. For even divide ratios, twice the desireddivide ratio can be loaded into the E016 and the TC output canfeed the clock input of a toggle flip flop to create a signaldivided as desired with a 50% duty cycle.A single E016 can be used to divide by any ratio from 2 to256 inclusive. If divide ratios of greater than 256 are neededmultiple E016s can be cascaded in a manner similar to thatalready discussed. When E016s are cascaded to build largerdividers the TCLD pin will no longer provide a means forloading on terminal count. Because one does not want toreload the counters until all of the devices in the chain havereached terminal count, external gating of the TC pins must beused for multiple E016 divider chains.LoadClock1001 00001001 0001•••1111 11001111 11011111 11101111 1111Load•••PE•••TCDIVIDE BY 113Figure 3. Divide by 113 E016 Programmable Divider WaveformsECLinPS and ECLinPS LiteDL140 — Rev 42–5MOTOROLA元器件交易网www.cecb2b.comMC10E016 MC100E016Applications Information (continued)EL01Q0 –> Q7LOCEE016LSBCLKTCPECEQ0 –> Q7PEE016CEQ0 –> Q7PEE016CEQ0 –> Q7PEE016MSBCLKTCEL01CLKTCEL01CLKTCPO –> P7CLOCKPO –> P7PO –> P7PO –> P7Figure 4. 32-Bit Cascaded E016 Programmable DividerFigure 4 on the following page shows a typical blockdiagram of a 32-bit divider chain. Once again to maximize thefrequency of operation EL01 OR gates were used. For lowerfrequency applications a slower OR gate could replace theEL01. Note that for a 16-bit divider the OR function feeding thePE (program enable) input CANNOT be replaced by a wire ORtie as the TC output of the least significant E016 must also feedthe CE input of the most significant E016. If the two TC outputswere OR tied the cascaded count operation would not operateproperly. Because in the cascaded form the PE feedback isexternal and requires external gating, the maximum frequencyof operation will be significantly less than the same operationin a single device.Maximizing E016 Count FrequencyThe E016 device produces 9 fast transitioning single endedoutputs, thus VCC noise can become significant in situationswhere all of the outputs switch simultaneously in the samedirection. This VCC noise can negatively impact the maximumfrequency of operation of the device. Since the device doesnot need to have the Q outputs terminated to count properly,it is recommended that if the outputs are not going to be usedin the rest of the system they should be left unterminated. Inaddition, if only a subset of the Q outputs are used in thesystem only those outputs should be terminated. Notterminating the unused outputs will not only cut down the VCCnoise generated but will also save in total system powerdissipation. Following these guidelines will allow designers toeither be more aggressive in their designs or provide themwith an extra margin to the published data book specifications.MOTOROLA2–6ECLinPS and ECLinPS LiteDL140 — Rev 4元器件交易网www.cecb2b.comMC10E016 MC100E016OUTLINE DIMENSIONSFN SUFFIXPLASTIC PLCC PACKAGECASE 776–02ISSUE D0.007 (0.180)UMB-N-Y BRKDZ-L--M-TL–MMSNSS0.007 (0.180)TL–MNSW281DXVIEW D-DG10.010 (0.250)SVTL–MSNSAZR0.007 (0.180)0.007 (0.180)MTL–MTL–MSNNSH0.007 (0.180)MTL–MSNSMSSCGG10.010 (0.250)SE0.004 (0.100)J-T-SEATINGPLANEK1KFVIEW S0.007 (0.180)MVIEW STL–MSTL–MSNSNSNOTES:1.DATUMS -L-, -M-, AND -N- DETERMINEDWHERE TOP OF LEAD SHOULDER EXITSPLASTIC BODY AT MOLD PARTING LINE.2.DIM G1, TRUE POSITION TO BE MEASUREDAT DATUM -T-, SEATING PLANE.3.DIM R AND U DO NOT INCLUDE MOLD FLASH.ALLOWABLE MOLD FLASH IS 0.010 (0.250)PER SIDE.4.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.5.CONTROLLING DIMENSION: INCH.6.THE PACKAGE TOP MAY BE SMALLER THANTHE PACKAGE BOTTOM BY UP TO 0.012(0.300). DIMENSIONS R AND U AREDETERMINED AT THE OUTERMOSTEXTREMES OF THE PLASTIC BODYEXCLUSIVE OF MOLD FLASH, TIE BARBURRS, GATE BURRS AND INTERLEADFLASH, BUT INCLUDING ANY MISMATCHBETWEEN THE TOP AND BOTTOM OF THEPLASTIC BODY.7.DIMENSION H DOES NOT INCLUDE DAMBARPROTRUSION OR INTRUSION. THE DAMBARPROTRUSION(S) SHALL NOT CAUSE THE HDIMENSION TO BE GREATER THAN 0.037(0.940). THE DAMBAR INTRUSION(S) SHALLNOT CAUSE THE H DIMENSION TO BESMALLER THAN 0.025 (0.635).DIMABCEFGHJKRUVWXYZG1K1INCHESMINMAX0.4850.4950.4850.4950.1650.1800.0900.1100.0130.0190.050 BSC0.0260.0320.020— 0.025— 0.4500.4560.4500.4560.0420.0480.0420.0480.0420.056— 0.0202° 10° 0.4100.4300.040—MILLIMETERSMINMAX12.3212.5712.3212.574.204.572.292.790.330.481.27 BSC0.660.810.51— 0.— 11.4311.5811.4311.581.071.211.071.211.071.42— 0.502° 10° 10.4210.921.02—ECLinPS and ECLinPS LiteDL140 — Rev 42–7MOTOROLA元器件交易网www.cecb2b.comMC10E016 MC100E016Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, andspecifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motoroladata sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights ofothers. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or otherapplications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injuryor death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorolaand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an EqualOpportunity/Affirmative Action Employer.How to reach us:USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609INTERNET: http://Design–NET.comJAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., . 852–26629298MOTOROLA◊2–8*MC10E016/D*MC10E016/DECLinPS and ECLinPS LiteDL140 — Rev 4
