Floating-point adder circuitry

专利名称：Floating-point adder circuitry发明人：Tomasz Czajkowski申请号：US14019196申请日：20130905公开号：US09405728B2公开日：20160802

专利附图：

摘要：An integrated circuit is provided that performs floating-point addition orsubtraction operations involving at least three floating-point numbers. The floating-pointnumbers are pre-processed by dynamically extending the number of mantissa bits,determining the floating-point number with the biggest exponent, and shifting the

mantissa of the other floating-point numbers to the right. Each extended mantissa has atleast twice the number of bits of the mantissa entering the floating-point operation. Theexact bit extension is dependent on the number of floating-point numbers to be added.The mantissas of all floating-point numbers with an exponent smaller than the biggestexponent are shifted to the right. The number of right shift bits is dependent on thedifference between the biggest exponent and the respective floating-point exponent.

申请人：Altera Corporation

地址：San Jose CA US

国籍：US

更多信息请下载全文后查看