MT92101
IP Phone ProcessorPreliminary Information
Features
•••••••••
Low Voltage Operation, 1.65 to 1.95 VoltsStandard 3.3 Volt Signal InterfacesOn-chip RISC CPU and Powerful DSPStandard Integrated System InterfacesEmbedded Physical Layer Firmware
G.729.AB and G.723.1A Vocoders, includingVAD and CNG*
Group 3 Fax Relay, 2400 – 14400 bpsH.323, MGCP, or SIP Protocol SoftwareAvailable
JTAG Port for Debug and Boundary Scan
DS5251
ISSUE 1
February 2000
Ordering InformationMT92101A/PR/BP1R 288 Ball PBGAMT92101A/PR/GP1R 208 Pin QFP-40°C to +85°CDescription
The MT92101 IP Phone Processor provides a highlyintegrated solution for an IP phone for use inenterprise applications. The IP Phone Processorintegrates an ARM-Thumb RISC CPU andsupporting subsystem including dual Ethernet MACand bridge, together with an OAKDSPCoreTM, fullRAM and ROM and a supporting subsystem.Firmware is embedded to allow the implementationof multi-channel voice compression, echo cancel-lation and supporting functions on the DSP.
Applications
•
Voice over IP Enterprise Telephones andRelated Equipment
* subject to patent indemnification
JTAG TEST + DEBUGDEBUGTESTJTAGVDDTDO423JTAGUSBPKMTHUMBCPUICEBREAKERUARTSSIOINTDMAGP TIMOAKDSPOCEMMEMORYINTERFACEDES802.1/p/d/QBRIDGEBµILDWATCHTDM Master3ADDRDATA162255TDMAUDIOAEC3538DMAINTC-busINTERFACERAM7k Data4k Prog6ROM8k Data60k Prog3282634GIOKEYPDMII10/100 MAC18MII10/100 MACEXTERNALMEMORYINTERFACEBOOT16PLLGND5nRESETEXTMASTSELECT ENABLEFigure 1 - Functional Block Diagram1
35CLOCK/OSC/PLL元器件交易网www.cecb2b.com
MT92101Preliminary Information156SERSEL_0SERCLKSERSEL_2SERSEL_3OPVDDSERDATASERSEL_1SERSEL_4OPGNDASCLKATFSADTARFSADRSERSEL_5TXEN1TXER1OPVDDOPGNDTXCLK1TXD1_3TXD1_2TXD1_1TXD1_0LAVDDLAGNDRXER1RXD1_3RXD1_2RXD1_1RXD1_0RXCLK1RXDV1CRS1COL1MDCMDIOOPVDDOPGNDTXEN2TXER2TXCLK2TXD2_3TXD2_2TXD2_1RXER2TXD2_0RXD2_3RXD2_1RXD2_2RXD2_0RXCLK2ADDR_21ADDR_20ADDR_19ADDR_17ADDR_18OPVDDADDR_16ADDR_15ADDR_14OPGNDADDR_13ADDR_12ADDR_11ADDR_10ADDR_9OPGNDOPVDDADDR_8ADDR_7ADDR_6ADDR_5ADDR_4ADDR_3ADDR_2LAGNDLAVDDADDR_1OPGNDOPVDDADDR_0nUBnOEnWE_0OPGNDOPVDDnWE_1DATA_15DATA_14DATA_13DATA_12Data_11DATA_10OPGNDDATA_9DATA_8OPVDDDATA_7DATA_5DATA_6DATA_4DATA_3DATA_21541521501481461441421401381361341321301281261241221201181161141121101081061041581021601001629816496166 168170901728817486176841788218018278184761867418872190701926819466196641986220060202582045620654208246810121416182022242628303234363840424446485052 9492OPVDDDATA_1DATA_0nCS_0RNWOPGNDnCS_1nCS_2nCS_3LCDSTRBOPGNDBGNTOPVDDBREQGPIO_31_MSCLKGPIO_30_MRFSGPIO_29_MTFSGPIO_28_MDRGPIO_27_MDTGPIO_4GPIO_3LAVDDUCLKOUCLKLAGNDUSBDPUSBDMGPIO_14_OAKGIO_8GPIO_13_OAKGIO_7GPIO_12_OAKGIO_6GPIO_11_OAKGIO_5GPIO_10_OAKGIO_4GPIO_9_OAKGIO_3GPIO_8_OAKGIO_2OPGNDOPVDDGPIO_7_OAKGIO_1GPIO_6_OAKGIO_0GPIO_25_PKCLKGPIO_24_PKFSGPIO_23_PKDRGPIO_22_PKDTGPIO_21_PWMGPIO_5GPIO_1_DEBUGPLLGNDLAVDDLAGNDPLLVDDAT1MCLKOMCLK208 PIN MQFP802
RXDV2CRS2n/cCOL2INT_0n/cINT_1nWDOGENGPIO_26_WDOGOUTGPIO_20_DPDSRGPIO_19_DPRTSGPIO_18_DPCTSGPIO_17_DPDTROPGNDOPVDDGPIO_16_DPDCDGPIO_15_DPRIDPRXDPTXINT_5LAGNDLAVDDINT_4INT_3INT_2TESTnRESETKEYIO_0KEYIO_1KEYOUT_0KEYOUT_1KEYOUT_2KEYOUT_3KEYOUT_4KEYOUT_5KEYOUT_6KEYOUT_7GPIO_0GPIO_2KEYIN_0OPGNDOPVDDKEYIN_1KEYIN_2KEYIN_4KEYIN_3TDOKEYIN_5TCKTMSTDInTRSTFigure 2 - Pin Description元器件交易网www.cecb2b.com
Preliminary Information288 PIN PBGA22212019181716151413121110987654321ABCDEFGHJKLMNPRTUVWYAAABMT92101Ball288 pinPBGAE3E4E19E20E21E22F1F2F3F4F19F20F21F22G1G2G3G4G19G20G21G22H1H2H3H4H19H20H21H22J1J2J3J4J19J20J21J22K1K2K3K4K19K20K21K22L1L2L3L4L19L20L21L22M1M2M3M4M19M20M21M22N1N2N3N4N19N20N21Pin NameBall288 pinPBGAN22P1P2P3P4P19P20P21P22R1R2R3R4R19R20R21R22T1T2T3T4T19T20T21T22U1U2U3U4U19U20U21U22V1V2V3V4V19V20V21V22W1W2W3W4W5W6W7W8W9W10W11W12W13W14W15W16W17W18W19W20W21W22Y1Y2Y3Y4Y5Y6Pin NameBall288 pinPBGAY7Y8Y9Y10Y11Y12Y13Y14Y15Y16Y17Y18Y19Y20Y21Y22AA1AA2AA3AA4AA5AA6AA7AA8AA9AA10AA11AA12AA13AA14AA15AA16AA17AA18AA19AA20AA21AA22AB1AB2AB3AB4AB5AB6AB7AB8AB9AB10AB11AB12AB13AB14AB15AB16AB17AB18AB19AB20AB21AB22Pin NameBall288 pinPBGAA2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22B1B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22C1Pin NameBall288 pinPBGAC2C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22E1E2Pin NameRNWDATA_0nCS_1nCS_3BREQGPIO_30_MRFSGPIO_28_MDRGPIO_3UCLKGPIO_14_OAKGIO_8GPIO_13_OAKGIO_7GPIO_11_OAKGIO_5GPIO_9_OAKGIO_3GPIO_7_OAKGIO_1GPIO_25_PKCLKGPIO_23_PKDRGPIO_21_PWMGPIO_5PLLGNDAT1nTRSTDATA_3DATA_1nCS_0nCS_2LCDSTRBGPIO_31_MSCLKGPIO_29_MTFSGPIO_4UCLKOUSBDPGPIO_12_OAKGIO_6GPIO_10_OAKGIO_4GPIO_8_OAKGIO_2GPIO_6_OAKGIO_0GPIO_24_PKFSGPIO_22_PKDTGPIO_1_DEBUGLAGNDPLLVDDMCLKTDIDATA_6DATA_2OPVDDOPGNDLAGNDBGNTCA_8GPIO_27_MDTLAVDDUSBDMCA_12CA_14DBGPIPROGnCDIRESETNOPGNDLAVDDMCLKOLAVDDTMSTDODATA_5DATA_4LAVDDOPGNDLAVDDOPVDDOPVDDOPGNDCA_9LAGNDCA_10CA_11CA_13CA_15OPGNDOPVDDBOOTPnABORTNOPVDDTIDDQTCKKEYIN_3DATA_8DATA_7CA_6OPGNDOPVDDKEYIN_5KEYIN_4KEYIN_2DATA_10DATA_9OPVDDOPVDDBCLKLAGNDKEYIN_1KEYIN_0DATA_12Data_11LAGNDCA_5OPGNDOPGNDGPIO_2GPIO_0DATA_13DATA_14OPGNDCA_4OPVDDKEYOUT_7KEYOUT_6KEYOUT_5nWE_1DATA_15CA_3OPVDDXDIAG_3KEYOUT_4KEYOUT_3KEYOUT_2nOEnWE_0OPGNDCA_2XDIAG_1XDIAG_2KEYOUT_1KEYOUT_0ADDR_0nUBCA_1OPVDDOPGNDKEYIO_1KEYIO_0nRESETADDR_1ADDR_2LAVDDOPGNDOPVDDXDIAG_0INT_2TESTADDR_3ADDR_4CA_0LAGNDCBUS_0LAVDDINT_4INT_3ADDR_5ADDR_6nCDRNnCBRNLAGNDDPRXDPTXINT_5ADDR_7ADDR_8OPVDDOPVDDCBUS_1OPVDDGPIO_16_DPDCDGPIO_15_DPRIADDR_9ADDR_10nCDWNOPGNDCBUS_2CBUS_3GPIO_18_DPCTSGPIO_17_DPDTRADDR_11ADDR_12OPGNDOPGNDOPGNDLAVDDGPIO_20_DPDSRGPIO_19_DPRTSADDR_13ADDR_15OPVDDLAVDDCBUS_4INT_0nWDOGENGPIO_26_WDOGOUTADDR_14ADDR_18ADDR_20LAGNDLAGNDOPGNDOPVDDOPGNDnCPWNLAVDDCBUS_14CBUS_13OPGNDCBUS_11CBUS_10CBUS_9OPGNDCBUS_8CBUS_7CBUS_5COL2INT_1ADDR_16ADDR_17LAVDDnCPRNOPVDDOPGNDOPVDDSERSEL_5TXCLK1CBUS_15LAGNDOPVDDCBUS_12COL1OPVDDTXD2_3CBUS_6LAVDDLAGNDLAGNDn/cn/cADDR_19ADDR_21SERSEL_2SERSEL_3SERSEL_4ATFSARFSTXEN1TXD1_3TXD1_1RXER1RXD1_1RXCLK1CRS1MDIOTXER2TXD2_2RXER2RXD2_1RXD2_0RXCLK2CRS2SERSEL_0SERCLKSERDATASERSEL_1ASCLKADTADRTXER1TXD1_2TXD1_0RXD1_3RXD1_2RXD1_0RXDV1MDCTXEN2TXCLK2TXD2_1TXD2_0RXD2_3RXD2_2RXDV2Figure 3 - Pin Description
Connection List
FunctionTDM AUDIOCLOCK/PLLMAC 1MAC 2Direct551816MultiplexedPin NamesASCLK, ARFS, ATFS, ADR, ADTMCLK, MCLKO, UCLK, UCLKO, AT1TXD1[3:0], TXER1, TXEN1, TXCLK1, RXD1[3:0], RXER1, RXDV1,RXCLK1, COL1, CRS1, MDC, MDIORXCLK2, COL2, CRS2,TXD2[3:0], TXER2, TXEN2, TXCLK2,RXD2[3:0],RXER2, RXDV23
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MT92101Connection List (continued)
FunctionEXT MEM INTTDM MASTERWATCHDOGKEYPADGPIOPKMINTERRUPTGP TIMSSIOUARTUSBJTAG/TEST/DEBUGRESETEXTERNAL BUSMASTERPOWERGROUNDNCTOTALDirect48011632060822612QFP:19BGA:34QFP:19BGA:342208 Pins / 238 Balls{1}{6}{1}{4}{5}{1}MultiplexedPreliminary InformationPin NamesDATA[15:0], ADDR[21:0], NCS[3:0], LCDSTRB, NOE, NWE[1:0],RNW, NUB{MSCLK, MRFS, MTFS, MDR, MDT}WDOGEN, {WDOGOUT}KEYOUT [7:0], KEYIN[5:0], KEYIO[1:0]GPIO[13:0] directly, GPIO[31:14] via multiplex with other signals{PKCLK, PKFS, PKDR, PKDT}INT[5:0]{PWM}SERCLK, SERDATA, SERSEL[5:0]DPRX, DPTX, {DPDSR, DPRTS, DPCTS, DPDTR, DPDCD, DPRI}USBDP, USBDMTMS, TCK, TDI, TDO, NTRST, TEST, {DEBUG}NRESETBREQ, BGNTVDD, VIOGNDNO CONNECTIONNote: A number of secondary signals are multiplexed with higher GPIO signals to allow some user flexibility.The development version of the part provides the following pins in addition to those on the production part:
FunctionC-BUS INTERFACEOCEM CONFIG/CONTROLCPU DIAGNOSTICSIDDQ TESTDEVELOPMENTTOTALDirect37551286 BallsMultiplexedPin NamesCBUS[15:0], CA[15:0], CPWN, CPRN, CDWN, CDRN, CBRNDBGP, BOOTP, IPROG, CDIRESETN, ABORTNBCLK, XDIAG[3:0]TIDDQ4
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Preliminary InformationOverview
The CPU subsystem supports guaranteed operationat up to 25MHz and the DSP subsystem at up to60MHz (60 MIPs) from a 3.3V power supply.The device implements a flexible standard serialinterface (TDM/Audio) to the external voicesubsystem. The MT92101 is compatible with theMitel MT92303 dual CODEC, but may also be usedwith most third party CODECs.
Multiple simultaneous full duplex voice channels canbe supported. The number of channels is limited bythe available DSP or CPU MIPs and is typicallydependant upon the speech compression and echocancellation algorithms selected. Fax transmissionsmay be relayed using a robust demodulation/remodulation scheme.
The device has been fully optimised for low poweroperation. It uses low power cell libraries, supportssoftware controlled low power modes for eachsubsystem and macrocell and fully implements localclock gating. The product is realised in three metallayer, small geometry, 0.35µm, CMOS technology.The next generation product, the MT92102, will berealised on very small geometry, four metal layer,0.18µm CMOS technology.
Note: The term ‘Word’ is used to represent 16- and32-bit numbers within this document. When used inthe context of the DSP subsystem a Word is a 16-bitnumber. When used in the context of the CPUsubsystem, a Word is a 32-bit number, with a 16-bitnumber being a half-Word.
CPU Subsystem
The ARM-Thumb CPU subsystem integrates theARM7-Thumb CPU together with a range ofperipherals chosen for this application. The MitelBµILD architecture is used to provide a robust,standard bus interface between each peripheralblock. Low power design techniques are used tosave power wherever possible.
The subsystem comprises the following blocks:•ARM-Thumb CPU,
•Synchronous Serial Interface,•TDM Master Serial Interface,•General Purpose Timer,
•
Universal Asynchronous Receiver/Transmitter,UART,
MT92101•
Quad Direct Memory Access Controller,(DMAC),
•USB Device Interface,
•802.1 Ethernet Bridge and Dual MAC,•DES Accelerator,
•32-bit General Purpose Input/Output,•Programmable Key Module Interface,•Keypad Scanner,•Interrupt Controller,•Watchdog Timer,
•External Memory Interface,
•Memory Interface (or ARM-OAK Interface, AOI),•Power Control,
•BµILD Broadcast Module,•Boot ROM, 1024 Byte.
Simple external bus mastership is supported to allowsharing of all external memory/peripheral resources.On-chip resources are not available to externalmasters.
ARM7-Thumb CPU
The ARM7-Thumb CPU is a high performance, lowpower, 32-bit RISC processor core and include ahardware instruction decompressor to support 16-bitinstruction half-Words. This core is based upon theproven ARM7 and retains its full 32-bit address,instruction and data Word widths. It contains a totalof 37 registers and supports 6 operating modes. Thecore supports a fast response to interrupts (4 to 28cycles) and all data processing instructions are fullyconditional. Operation with 16-bit instruction widthsis supported via a hardware decompressor operatingwith zero timing overhead (3-stage pipelinemaintained). Code size in this mode is typicallyreduced to 65% of the requirement for full 32-bitinstruction mode.
The core contains an ICEBreaker extension andJTAG interface to support non-intrusive debug. ThisJTAG interface also supports full boundary scanaccess.
In the MT92101, the ARM-Thumb may be clocked atup to 25MHz, although this is programmable (theMT92102 will be clocked at up to 40MHz). A lowpower sleep mode is supported.Synchronous Serial Interface
The CPU subsystem has a Synchronous SerialInterface, which typically controls a variety of devicesthat employ a Synchronous Serial Interface.Examples are serial EEPROMS, NVRAM, LCD and
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MT92101other display devices, CODEC and other voicecircuits. The interface is fully flexible and provides:•
MICROWIRETM Interface compatibility, to allowinterfacing to memory and peripheral devicessupporting this standard;
•
Serial Peripheral Interface (SPI) compatibility,an interface found on certain Motorola, TI andST microcontrollers;
•
data transfer with either Byte or Word orientedprotocols, with the Word width beingconfigurable from 2 to 32 bits;
•triple buffered Transmit and Receive Channels;•operation in either Interrupt or Polled mode;•support for up to 6 slave devices (i.e., 6 enablesignals, 1 clock and 1 bi-directional data);•
fly-by support for single addressed DMAtransfers.
TDM Master Serial Interface
The TDM Master Serial Interface included in theCPU subsystem is provided for use in tele-worker ornon-IP applications, where it becomes the mainsystem interface for voice data. The interface issubstantially the same as the TDM Audio interfacewithin the DSP subsystem, and is a fully flexiblemulti-channel PCM based interface that provides:•
a five pin interface (1 clock, RX and TX framesyncs, input data and output data); frame syncsand clock support programmable direction andpolarity;
•
single or multi-channel capability; themultichannel facility allows time division
multiplexing of the serial bitstream into up to 32channels. Any number of these channels canbe used for transmit or receive independently.The CPU must supply data for the transmit
channels in the correct order and sort data fromthe receive channel.
•compatibility with Mitel ST-Bus and most PCMbusses;
•
transmit and receive sections can operate withDMA from/to memory to reduce CPUinteraction;
•
inclusion of a compander circuit to support A-law andµ-law interfaces; when enabled, thecompanding operation is transparent to theCPU. The compander may also be accessedindependantly by the CPU to allow separatecompression and expansion operations, inparallel with companded or non-compandedserial IO.
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Preliminary InformationGeneral Purpose Timer
The CPU subsystem has a flexible general purposetimer that may be used for timing multiple events.Two identical independent timer/counter elementsare provided; each contains the following:•a 12-bit, variable prescaler generating thecounter clock;
•a 32-bit fully programmable up/down timer/counter;
•multiple counter modes including free running,halt-on-zero/overflow;
•four 32-bit compare registers;
•flexible interrupt generation from the timer and/or compare registers;
•
PWM signal output option using main counterand compare register 1.
Universal Asynchronous Rx/Tx, UART
A Universal Asynchronous Receiver Transmitter(UART) is included in the CPU subsystem, providingindustry standard levels of support for full-duplexasynchronous serial communications. It is typicallyused for communication with a PC for configurationor test purposes, but may also be used to implementan IRDA port. Features of the UART include:•full duplex operation, independent transmit andreceive channels;
•software configurable as either a DTE or DCE;•
fully programmable baud rate selection derivedfrom subsystem clock; all standard baud ratesup to and including 153.6 and 230.4 kbit/s aresupported within acceptable margins;
•theoretical limit for the interface of one half ofthe subsystem clock frequency;
•automatic baud rate and character formatdetection for received data;
•automated support of Hardware (RS-232C andRS-232E) and Software Flow Control;
•input filters for serial input data and modemcontrol inputs;
•
data formatting for 7 or 8 bit serial character, 1or 2 stop bits, and even, odd, mark, space or noparity;
•line break detection/generation;
•framing, overrun and parity errors, with interruptgeneration;
•
fly-by support for single addressed DMAtransfers.
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Preliminary InformationQuad Direct Memory Access Controller, DMACThe DMA Controllers allow data to be moved aroundthe subsystem with little CPU intervention. Each ofthe 4 controllers contains a pair of sub-controllers,each capable of managing a single addressed (fly-by) DMA transfer between memory and an implicitlyaddressed device, such as the UART. Alternatively, apair of sub-controllers may be used to perform dualaddressed transfers, where both source anddestination require address generation. A typicalapplication might allocate 4 sub-controllers tosupport the Ethernet Bridge, leaving 2 controllers (or4 sub-controllers) to support the UART, SSIO andany memory to memory transfers. Each controllersupports the following:•
transfer rates at up to 4 bytes per clock cycle,single addressed, 2 bytes per cycle, dualaddressed;
•transfer counts up to 64k items;
•block and packet transfer modes;
•chained transfers to support scatter-gatheroperations;
•
hardware or software triggered transfers.
USB Device Interface
A standard USB interface for connection to a PC orsimilar host is included, andhas the followingfeatures:•supports 8 programmable end points;•
has a 16-byte FIFO buffer per end point.
802.1 Ethernet Bridge and Dual MAC
The 802.1 Ethernet Bridge and Dual MAC allowsconnection of a desktop workstation (PC) to a LANthrough the IP telephone; one port connects to theLAN, the other to the workstation. Using dual ports inthis way avoids the need for a dedicated LAN port forthe telephone and also reduces cable bulk.
The MAC ports support 10Base-T and 100Base-TXEthernet formats and have standard MII interfaces toexternal PHYs. FIFO buffers are inserted in transmitand receive paths between each MAC and theswitch. Input buffers are 3328 bytes deep to allow atleast 2 full packets to be accommodated, outputbuffers are 1536 bytes deep, accommodating at least1 full packet. The switch allows packet injection andpacket extraction for communication with the phone.A watchdog counter allows the splitting of packettransfers through the switch to avoid problems withCPU/bus sharing.
MT92101DES Accelerator
The DES Accelerator is a hardware accelerator forexecution of the Data Encryption Standard (DES)algorithm as defined in FIPS PUB 46-1, which isequivalent to the Data Encryption Algorithm (DEA)provided in ANSI x3.92-1981. Standard DES isexecuted in just 16 clock cycles; cipher blockchaining (CBC) is supported and related DESalgorithms such as triple-DES and DES-X are alsosupported.
32-bit General Purpose Input/Output
The General Purpose I/O is a set of up to 32 signalsthat may be individually written to or read by the CPUfor general purpose control. Each signal isprogrammable for direction (input or output) and pull-resistors may be selectively disabled. Nine of thesesignals may be configured such that they arecontrolled directly from the DSP. Most GeneralPurpose I/O (GPIO) pins have internal pull-resistorsto either VIO or GND, split roughly equally; a fewGPIO pins have no pull-resistors. Therefore,individual GPIO signals may be selected in order tominimize static current consumption in theapplication, based upon the known externalconditions.
A number of the GPIO signals are multiplexed withother functions in order to reduce pincount.Multiplexing is controlled from the CPU and aminimum of 14 GPIO signals are always available.Programmable Key Module Interface
The Programmable Key Module Interface is a simpleserial interface intended to support a specializedKEY and LED expansion port, which is required insome systems. The features include the following:•a 4-wire interface: output clock, output framemarker, output data and input data;
•ability to send 16 bytes of control and receive16 bytes of status information per frame;
•
a programmable clock divider from subsystemclock, to facilitate low frequency operation(typically 3kHz).
Because the PKM interface signals are mulitplexedwith GPIO pins and the interface may be powereddown, it may be disabled in systems where it is notrequired.
Keypad Scanner
The flexible keypad interface supports keypadconfigurations of up to 8x8 keys (e.g., 10x6, 9x7,
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MT921018x8). There are 8 row outputs, 6 column inputs and 2programmable row/column IOs. Keypad scanninginvolves reading the input register and interpreting itbased on the driven output state. Interrupts may bemasked on a per input basis. Key debounce, ifrequired, must be handled in software.Interrupt Controller
The Interrupt Controller block manages all internallygenerated CPU subsystem interrupts, plus 6 externalinterrupts. It translates interrupts into regular IRQsand fast, higher priority FIQs for the ARM-ThumbCPU. A hardware priority scheme is used tominimize interrupt latency. Each interrupt source maybe individually configured for the following:•polarity, active high or low;•enabled or disabled;•edge or level sensitivity;•
interrupt type, IRQ or FIQ.
Watchdog Timer
The watchdog timer ensures that system lock-updoes not occur due to hardware or run-time softwareerrors. It is driven from the CPU subsystem clockand contains a 32-bit primary counter and an 8-bitsecondary counter with prescaler. These countersare user programmable, allowing control of thewatchdog CPU interrupt rate and of the time durationin which this interrupt must be cleared. Any lock-upsituation would be cleared via a system resetgenerated on time-out of the secondary counter.The timer may be disabled for debug or similarreasons via a control pin. An output is provided forpower-down or disabling of external functions duringwatchdog time-out.
External Memory Interface
The External Memory Interface is the interfacebetween the on-chip BµILD bus and any externalmemory and peripherals. It performs byte and half-Word packing and sub-bus width writes to allow anyon-chip bus master to access 8- or 16-bit externalcomponents. The external interface consists of 16data pins, 22 address pins, 5 select pins, and 4control/enable signals. It can address up to 4 Mbytesof memory in 5 separate areas. Each area may beindependently configured for memory/peripheral typeand number of start/access/stop wait states (0 to15). One area is dedicated to LCD control andtherefore, generates a strobe signal in place of thenormal chip select. Zero wait state operation at themaximum specified operating frequency is supportedfor devices having a 10nS access time or better.
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Preliminary InformationMemory Interface (AOI - ARM-OAK Interface)The Memory Interface allows the DSP to access theCPU’s memory map, including all off-chip memory. Afixed 16 kWord window in the DSP’s data memorymap may be mapped to any position within theCPU’s memory map via a programmable BASEADDRESS. This window is termed ‘shared memory’.Two separate BASE ADDRESS registers, oneaccessible from the CPU and one from the DSP, areimplemented. The BASE ADDRESS is defined bythe contents of one of these registers, with selectionbeing controlled by the CPU.
In order to minimize latency, by default the MemoryInterface is the highest priority master on the BµILDbus. However, the relative priorities of the MemoryInterface and each of the 2 DMA Controllers may befully software configured via the SystemConfiguration Register.
Three modes of operation are supported for datatransfer across the AOI. The simplest mode, suitablefor limited data transfers at slow speed only,generates wait states to the DSP during transfers. Asthe DSP is typically operating faster than the CPUthis results in significant lost time to the DSP.The second mode, READ AHEAD, stores the currentaccessed address in a local register and returns datafrom the previous access. The new data is then readfrom memory and stored in the Memory Interfaceready for the next READ AHEAD cycle. Thismechanism avoids any DSP waits, at the expense ofa single sample latency, and is not suitable fortransferring large blocks of data.
The third mode, DMA, allows fast transfer and wouldbe the mechanism chosen for transferring largerblocks of data. Blocks of data up to the full 16 kWordshared memory area may be transferred with noCPU or DSP intervention once the transfer isinitiated. A DSP interrupt is generated when thetransfer is complete.
Inter-processor communication through the AOI usesa pair of registers: the CPU status register (writableby the CPU only, readable by both processors) andthe DSP status register (writable by the DSP only,readable by both processors). Each contains aninterrupt bit, 3 associated interrupt type bits, a readybit and 4 additional general purpose bits that may beused to implement a polling mechanism.
The AOI transfers data between the asynchronousclock domains of the 2 processors. Itsimplementation relies upon the DSP being clocked at
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Preliminary Informationtwice the rate of the CPU (or greater) to guaranteecorrect operation.Power Control
The Power Control block allows selection of powerstates (enabled or disabled) for each CPUsubsystem peripheral during STANDBY and RUNpower modes. All CPU subsystem peripherals maybe powered down in this way, although some coreactivity remains in the key blocks (External MemoryInterface, BµILD Broadcast Module, WatchdogTimer, and within this block). The Power Controlblock also contains a control bit to allow selection ofSTANDBY mode.
BµILD Broadcast Module
The BµILD Broadcast Module block performs anumber of functions essential to operation of theBusforµControllerIntegration inLow-powerDesigns(BµILD).•bus master arbitration,•control of bus modes,
•
hardware system debug support and diagnosticgeneration,
•stores system configuration data,
•handshaking to allow external bus masterhip.System configuration data includes clock selection,PLL programming, bus master prioritization andDMA assignment.
External bus masters are supported via a simpletwo-pin handshaking mechanism. Upon grantingexternal bus mastership, all the external memoryinterface pins (address, data, chip select andenables) are tri-stated. The external bus master maythen access any external memory or other peripheraldevices. However, the interface does not supportexternal bus master accesses of on-chip memory orperipherals.Boot ROM
Application boot normally runs directly from externalROM/FLASH at location 0x00000000. Alternatively, ifpin GPIO[0] is held low on exit from system reset,boot occurs from the internal boot ROM (FLASHLoad Mode). The internal ROM contains a simplealgorithm to allow download and execution of a user-defined program directly from the UART. Typicallyduring a FLASH Load, this program will download fullapplication code via the UART and program it intothe on-board FLASH ROM during end productmanufacture or field re-program. Alternatively, in
MT92101situations where full debug tools are not appropriate,test software could be downloaded.CPU Memory Map
Address space is split into 8 equal segments,decoded from the top 3 address lines. The bottom 6segments form the main memory areas for theinternal Boot ROM and the 5 external memory areas.The next segment is reserved and the final area isused for all internal memory mapped registers. Thisfinal segment is further subdivided into sub-segments, each of 1024 Words, with all memory-mapped blocks being allocated one sub-segment.
Reserved, Test Access Only0xE0030000→ 0xE03FFFFEthernet MAC 20xE002 E000→ EFFFEthernet MAC 10xE002 D000→ DFFF802.1 Ethernet Bridge0xE002 C000→ CFFFUSB Device Interface0xE002 A000→ AFFFProgrammable Key Module0xE002 9000→ 9FFFSynchronous Serial Interface0xE002 7000→ 7FFFGeneral Purpose Timer0xE002 6000→ 6FFFKeypad Scanner0xE002 5000→ 5FFFGeneral Purpose IO0xE002 4000→ 4FFFMemory Interface (AOI)0xE002 0000→ 0FFFTDM Master SIO0xE001 C000→ CFFFUART0xE001 8000→ 8FFFDMAC 20xE000 D000→ DFFFDMAC 10xE000 C000→ CFFFExternal Memory Interface0xE000 8000→ 8FFFInterrupt Controller0xE000 6000→ 6FFFPower Control0xE000 5000→ 5FFFWatchdog Timer0xE000 4000→ 4FFFBuILD Broadcast Module0xE000 2000→ 2FFFReserved, Test Access Only0xE000 0000→ 0FFFTable 1. CPU Subsystem Memory Mapped
RegistersFurther details of this allocation and of all registerbits are described in a separate publication,MT92101 IP Phone Processor Handbook, DM5252.Each main memory area may address up to 512Mbytes (ADDR[28:0]). However, this is limited to just4Mbytes (ADDR[21:0]), due to the number ofaddress pins available on the MT92101. Any attemptto access memory outside of this range will accesscopied images of the 4Mbyte areas.
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MT92101The lower 3 external memory areas are nominallyallocated to ROM (External Mem 1), RAM (ExternalMem 2) and EEPROM (External Mem 3). The topexternal memory area is dedicated to an LCDcontroller. The positions of Internal Boot ROM andExternal Mem 1 (ROM) or of Internal Boot ROM andExternal Mem 2 (RAM) may be swapped undersoftware control via the System ConfigurationRegister. Alternatively, the positions of Internal BootROM and External Mem 1 (ROM) will be swapped ifpin GPIO[0] is held high during device reset. Thesefeatures allow the CPU to boot from internal ROM orfrom external ROM, or to execute code resident inRAM in a flexible manner. Apart from theselimitations, each external memory area may used tomap any type of memory or peripheral.
Reserved0xFFFFFFFF0xE0400000Mem Map Registers0xE03FFFFF0xE00000000xDFFFFFFF0xC0400000Reserved0xC03FFFFF0xC00000000xBFFFFFFF0xA0400000External Mem 5 (LCD)0xA03FFFFF0xA00000000x9FFFFFFF0x80400000External Mem 4 (Spare)0x803FFFFF0x800000000x7FFFFFFF0x60400000External Mem 3 (EEPROM)0x603FFFFF0x600000000x5FFFFFFF0x40400000External Mem 2 (RAM)0x403FFFFF0x400000000x3FFFFFFF0x20400000External Mem 1 (ROM)0x203FFFFF0x200000000x1FFFFFFF0x00000400Internal Boot ROM0x000003FF0x00000000Table 2. CPU Subsystem Memory MapCPU Power Modes
The CPU subsystem supports 2 main operatingmodes: normal operating (or RUN mode) and lowpower (or STANDBY mode). The power state of eachblock within the CPU subsystem may beprogrammed individually in both modes. STANDBYmode is entered via software control, with exit toRUN mode occurring via an interrupt or system resetonly.
An alternative power saving mechanism may beused when the CPU is not required, but when otherbus masters (Memory Interface and DMAC) mayrequire access to the bus. This mechanism is knownas SLEEP mode and utilizes a coprocessor
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Preliminary Informationinstruction to fully suspend the ARM-Thumb, withwake-up into RUN mode again occurring via aninterrupt or system reset.
DSP Subsystem
The DSP subsystem integrates the OAKDSPCoreTMwith a range of peripherals and memory to supportall physical layer processing. A dual phase clockingscheme is used to maximize performance whilemaintaining a low power solution. The subsystemcomprises the following blocks:•OAKDSPCoreTM,•OCEM,
•Memory Interface (AOI),
•C-bus Interface (to support full debug),•TDM Audio Serial Interface,
•Acoustic Echo Canceller (via firmware upgrade),•Direct Memory Access Controller, DMAC,•Interrupt Controller,
•Bus Interface Unit (BIU),
•Clock Generation (ACLK and CLKGEN),•Data RAM, 7 kWord,•Data ROM, 8 kWord,
•Program ROM, 60 kWord,•
Program RAM, 4 kWord.
OAKDSPCoreTM
The OAKDSPCoreTM is a high performance, 16-bitfixed point DSP core. It contains a 36-bit ALU, plusfour 36-bit accumulators, and includes a bitmanipulation unit containing a 36-bit left/right barrelshift. The core utilizes a software stack.
In the MT92101, the OAK is clocked at 60 MHz toprovide a maximum of 60 DSP MIPS, although this isprogrammable. In the MT92102, the OAK will beclocked at 90MHz. The core has low power sleepmodes.OCEM
Debug is supported via anOn-ChipEMulation circuit(OCEM), accessed via the external parallel C-bus orvia the CPU JTAG port and the Memory Interface.Five device pins are required for selection andcontrol of the various emulation boot modes, and areonly provided on the development pinned device.Note: DSP debug access through the JTAG port andMemory Interface is currently limited.
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Preliminary InformationMemory Interface (AOI, or ARM-OAK Interface)The AOI is the primary link between the CPU andDSP subsystems and is described in the CPUsubsystem part of this datasheet (see page 8).C-bus Interface
The C-bus interface is required to support full DSPdebug and is a 37-pin parallel interface giving accessto the combined (multiplexed) DSP data andprogram busses. The C-bus interface is onlyavailable on the development pinned device.TDM Audio Serial Interface
The TDM Audio Serial Interface is used fortransferring audio data to one or more voiceCODECs or similar devices. The interface issubstantially identical to the TDM Master interfacewithin the CPU subsystem and is a fully flexiblemulti-channel PCM based interface, which providesthe following:•a five pin interface (1 clock, RX and TX framesyncs, input data and output data);
•frame syncs and clock support programmabledirection and polarity;
•
single or multi-channel capability, allowing timedivision multiplexing of the serial bitstream intoup to 32 channels; any number of these
channels can be used for transmit or receiveindependently; the DSP must supply data forthe transmit channels in the correct order, andsort data from the receive channel;
•compatible with Mitel ST-Bus and most PCMbusses;
•
transmit and receive sections can operate withDMA from/to memory to reduce DSPinteraction; the DMA controller can beprogrammed with the number of Words totransmit or receive (up to 8192 Words each)and generates an interrupt when complete;•
a compander circuit is included to support A-law andµ-law interfaces. When enabled thecompanding operation is transparent to theDSP. The compander may also be accessedindependently by the DSP to allow separatecompression and expansion operations, inparallel with companded or non-compandedserial IO.
Acoustic Echo Canceller (AEC)
The AEC is achieved through a firmware upgradeand is a half-duplex DSP firmware solution. Itoperates in conjunction with the TDM Audio SerialInterface to cancel acoustic echo on a single,programmable, audio channel.
MT92101Direct Memory Access Controller (DMAC)The DMAC operates in conjunction with the TDMAudio Interface and the AOI to allow data to betransferred to or from the external voice CODECsand DSP data memory, and to or from the CPUsubsystem (usually shared external memory) andDSP data memory with no DSP intervention. Thehardware associated with this function is located inthe Bus Interface Unit and in the AOI.Interrupt Controller
The Interrupt Controller block manages all internallygenerated DSP subsystem interrupts, plus 2 externalinterrupts (sharing INT[5:4] pins with CPUinterrupts). The controller translates these to one ofthree interrupt priority levels to the OAKDSPCoreTMin a fully programmable way. Inputs are edgesensitive.
Bus Interface Unit
The Bus Interface Unit (BIU) controls all access tothe on-chip DSP data and program busses. Itproduces the C-bus and contains the DSP GPIO andDMA circuitry. It allows individual selection ofexternal C-bus program, data, mailbox and monitorprogram wait states. Power control for datamemories and peripherals is also managed from thisblock.
DSP Memory Map
The DSP data space contains 7kWords of RAM (2-kWord on-core XRAM, 2-kWord on-core YRAM and3-kWord off-core XRAM) plus 8-kWords ROM forstorage of data tables and filter coefficients. Another16-kWords is allocated to shared memory, 1-kWordsto an external emulation mailbox, 1-kWords toexternal file IO and 4-kWords to memory mappedregisters. A 16-kWord window is available forexternal C-bus access to support development. Eachmemory-mapped block is assigned its own 256-Wordwindow.
The DSP program space contains 59-kWords ofapplication ROM plus 4-kWords of RAM to supportprogram patches and customisation. The remaining1kWord is reserved for an external monitor programto support emulation and debug. This programmemroy map is mirrored internally to allow aninternal monitor program to support enhanced debugvia the Memory Interface and JTAG port in the future.All of this space, with the exception of boot code,may be mapped to the C-bus for externaldevelopment use.
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MT92101On-core YRAM (2k)0xFFFF0xF800OCEM Mem Map Registers (16w)0xF7FF0xF7F0Reserved (2k-16w)0xF7EF0xF000External Memory (16k)0xEFFF0xB000Reserved0xAFFFMapped:0xA7E0Off-chipMailbox (992w)0xA7DF0xA400File IO (1k)0xA3FF0xA000Data ROM (8k)0x9FFF0x8000Shared Memory (16k)0x7FFF0x4000Reserved (4k)0x3FFF0x3000Mem Map Registers (4k)0x2FFF0x2000Reserved (3k)0x1FFF0x1400Off-core XRAM (3k)0x13FF0x0800On-core XRAM (2k)0x07FF0x0000Table 3. DSP Subsystem Data Memory MapAttempted access to internal program ROM (0x0000to 0xEFFF) via amovp instruction will be detectedand blocked by a program protection mechanism, toprevent unauthorised copying of embedded firmware.
BIU Boot (2w)0xFFFF0xFFFEApplication/Patch RAM (4k–2w)0xFFFDOn Chip0xF000Monitor (1k)0xEFFFOn or Off Chip0xEC00Boot Code (64w)0xEBFFOn Chip0xEBC0Application ROM (59k – 96w)0xEBBFOn or Off-chip0x0020IPROG = 1 or 0Interrupt Vectors (32w)0x001F0x0000Table 4. DSP Subsystem Program Memory MapAll ROM may be programmed during wafermetalisation to allow fast generation of code updatesand variants.DSP Power Modes
The DSP subsystem supports three operatingmodes: normal operation (or ACTIVE mode), lowpower IDLE mode, and lowest power STOP mode.The DSP is powered down in both IDLE and STOPmodes. In IDLE mode, the PLL remains active toallow a fast switch to ACTIVE mode. In STOP mode,the PLL is fully powered down and therefore, a timedelay is necessary to allow the PLL to lock and
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Preliminary Informationsettle. This time delay is automatically generated andwill be nominally 200µs for a 40MHz master clock,and proportionately longer for a slower clock.Exit from IDLE mode is normally made via aninterrupt, although it may also occur via a systemreset, a soft DSP subsystem reset, or a CDI reset.Exit from STOP mode normally is achieved undercontrol of the CPU via an OAK CONTINUE signal,generated by the AOI. Alternatively, an externalinterrupt, a system reset, a soft DSP subsystemreset, or CDI reset may be used. Exit from STOPmode is directly to ACTIVE mode. The OAKCONTINUE signal ensures that the DSPrecommences operation in exactly the same statefrom which it entered STOP mode (i.e., all registerstates are maintained).
Clock Provision and PLL ClockGeneration
The number of externally provided clocks isminimised, while offering sufficient flexibility to coverall possible applications. Two external, dedicatedclock sources are required:
•Master Clock (MCLK)
•USB Clock (UCLK), fixed at 48.000 MHz
MCLK provides the CPU Subsystem clock directlyand the TDM Clock via simple division. Two modesof operation are possible as described below:a)Internal TDM Clock
The master clock is limited to an integer multipleof the required TDM clock frequency. The TDMclocks are generated by dividing MCLK; theratio is programmable by the CPU (for the TDMMaster Interface) or the DSP (for the TDMAudio Interface).b)External TDM Clock
The master clock may be any frequency up to40MHz. TDM clocks are input to the serial inter-face clock pins.
Each USB clock may be driven from an off-chip logiclevel source, or may be generated via an on-chipcrystal oscillator (i.e., requiring 2 pins per clock, 4pins in total). MCLK must be active at all times toallow the CPU to wake from STANDBY mode,although UCLK may be externally disabled when theUSB is not being used, and when it is not selected asthe PLL clock source.
MCLK is typically used directly by the CPUsubsystem, but may be divided to lower powerconsumption; division ratios of 2, 4, 8 and 16 aresupported.
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Preliminary InformationThe DSP subsystem clock is generated from MCLKor UCLK via a fully embedded programmable PLL(n*0.25*CLK, up to 90MHz). It is generated through aprogrammable divide by 1 / 2 / 4, followed by a fullyprogrammable PLL giving integer multiplication. Afurther programmable divide by 1 / 2 stage after thePLL allows further flexibility. Clock source selectionfor the PLL is programmable by the CPU, althoughthe default is to MCLK. Changes to this clock sourcemay only be made while the DSP subsystem is inSTOP mode. When active, the DSP clock mustalways operate at least twice as fast as the CPUclock to allow correct operation of the AOI block. SeeFigure 3 for an illustration.
The reset pin, nRESET, utilises a power-on-resetcell, which may be used as the source of a reset forother devices. A single external component (acapacitor) is required to provide the appropriate timeconstant.
MT92101Multiple simultaneous voice channels can besupported, up to the 90 DSP MIP limit, dependentupon voice compression and audio echo cancellationrequirements.
Acoustic functions supported include DTMF/callprogress tone generation, acoustic echo cancellation,volume control and sidetone generation.
The host interface provides a communications linkbetween the DSP subsystem and the controllingCPU. All information passed between the twoprocessors is processed by this module.
All firmware modules are run within a simple RTOSthat handles all scheduling and prioritising of tasksand maximises usage of available DSP MIPS. Allfirmware modules have been extensively verifiedusing a combination of software simulation andhardware emulation.Firmware Feature List
The following features are supported in firmware:
Embedded DSP Firmware
The OAK subsystem has embedded full physicallayer firmware, including multi-channel voicecompression, acoustic functions and a host interface.
••G.729.AB compression;G.723.1A compression;
CPU Subsystem ClockMCLKOSCDIV1/2/4/8/16To TDM Interfaces(Division to GenerateTDM Clocks)ARMCLKDIVDSPSubsystemClockMCLKOMUXOSCUCLKOAKCLKSRCDIV 1/2/4PLL*1 TO *23DIV 1/2OAKCLKDIVOAKCLKMPYOAKPLLDIVDSP Subsystem STOPExit Time ClockUCLKOUSBOSCDISUSB Clock (48.00MHz)Note: All configuration via System Configuration RegisterFigure 3 - Clock Provision, Multiplexing and Division/MultiplicationMaster ClockMCLK10 MHz24.57640.9640USB ClockUCLK48 MHz484848CPU SubsystemClock10 MHz (MCLK)24.576 (MCLK)40.96 (MCLK)2.5 (MCLK / 16)DSP Subsystem Clock56.25 MHz (9 * ECLK / 4)60MHz (6 * MCLK)81.92 (2 * MCLK)STOPTDM Clock1 MHz (MCLK / 10)2.048 (MCLK / 12)4.096 (MCLK / 10)External - InactiveTable 5 - Example Clock Configurations13
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MT92101•VAD / CNG;
•audio echo suppression;
•DTMF / call progress tone detection andgeneration;
•sidetone and loopback;
•caller ID in-band signalling generation;•adaptive playout;•signal classifier;•
executive/RTOS.
CPU Software
Full software is provided for demonstration purposesand as the basis for a full system. The H.323, SIPand MGCP/MEGACO protocol stacks, if required,are available only as object code and have anassociated per-use license cost.
All software modules have been verified and arebelieved to support full interoperability with existingequipment. However, full independent verification/approval of this software has not yet been achieved.Software Feature List
The following features are available as softwaremodules:•protocol stacks: H.323, SIP and MGCP/MEGACO;
•RTP/RTCP transport layer;
•interface API to the DSP subsystem;
•reference phone application, including a basicMMI;
•BSP and hardware drivers associated with all ofthe above;
•
standard RTOS support for Precise/MQX fromPrecise Software Technologies Inc.
Alternative operating systems may also besupported, dependant upon customer requirements.Possibilities include pSOS from Integrated SystemsInc., Nucleus from Accelerated Technology Inc., andVxWorks from Wind River Systems.
Technology and Packaging
The MT92101 is realised in our well proven 0.35µmtriple layer metal CMOS technology, for earliestavailability of prototypes at minimum risk. This partsupports audio echo cancellation only as a firmwareupgrade to the DSP, and operates at maximum clockspeeds of 25MHz for the CPU subsystem and60MHz (MIPs) for the DSP subsystem. DSP access
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Preliminary Informationto external memory over the C-bus can reach40MHz, dependant upon memory speed. It isavailable in 208 pin TQFP, 28 x 28 x 1.4 mm, 0.5mmpitch, or in 288 ball (238 used ball) PBGA, 23 x 23 x1.2mm, 1mm pitch, package options.
A further package option is supported fordevelopment devices only. These developmentdevices use all connections on the above PBGApackage to provide access to the DSP combinedprogram and data buses (C-bus), to allow full DSPdebug and operation with external DSP memory.
Next Generation Realisation on 0.18µmTechnology, MT92102
The MT92102 will be realised in a very smallgeometry, 0.18µm, quad layer metal CMOStechnology for lowest cost and power consumptionand supports all features and parametricperformance outlined here. Additionally, theMT92102 will support fully audio echo cancellation,and will operate at greater maximum clock speeds.The MT92102 will be fully pin compatible with theMT92101, although it will be necessary to supply twopower supply voltages. The development device forthe MT92102 will have the ability to use externalprogram memory - zero-wait at up to about 50MHz,dependant upon memory speed, is included.
Development Support
The MT92101 is supported with a development/evaluation kit which includes two evaluation boardsand a comprehensive suite of software APIs,development tools and PC-based exercisers to allowthe rapid development of IP phone applications,SOHO gateways and similar applications. The kit willalso support the MT92102. The boards support fullCPU debug access and basic DSP debug access viaa JTAG interface. Full DSP debug access may beprovided optionally via a C-bus interface.H.323 Development Toolkit
An optional add-on software toolkit is available toprovide a full complement of H.323, including H.235and H.450 extensions.MGCP/MEGACO and SIP
Development toolkits for SIP and MGCP/MEGACOwill be available shortly.
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Preliminary InformationAbsolute Maximum Ratings*- Voltages are with respect to ground (GND) unless otherwise stated.
Parameter1234Any VDD Pin to any GND PinAny Signal Pin to GNDStorage Temperature RangeESDSymbolMin- 0.3- 0.3- 552Max2.5VDD + 0.51252UnitsVV˚CkVMT92101*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.Recommended Operating Conditions
Parameter123456789Operating voltage rangeaOperating temperature rangeInput high voltageInput low voltageInput pull-up/down currentInput currentInput capacitanceOutput high voltageOutput low voltageSymVDDOTVIHVILIIPU/IIPDIICINVOHVOLIOCOUT0.8*VDD0.4*VDD104033Min3.0-400.7*VDD0.3*VDD90510Typ‡3.3Max3.6+85UnitsV˚CVVµAµApFVVµApF0 < VIN < 3.60 < VIN < 3.6 All other inputsAll inputs and IO's|IOUT|=100 uA (microA)|IOUT|=100 uA (microA)All outputs and IO'sTotal external load, all outputsand IO'sTest ConditionsChip core power supply10Three-state leakage current11Output capacitancea. MT92102 will have an additional 1.8V nominal power supply.Electrical Characteristics†
Characteristics123456Clock input frequencyClock input frequencyClock input ratioClock input ratioCrystal load capacitanceCrystal start timeSymMCLKUCLKMCLKUCLKMinTyp‡Max25UnitsMHzMHz%%pFmSTest ConditionsCPU subsystem frequencyUnity input ratioDigital input 25 MHzDigital input 48 MHzMCLK and UCLKMCLK and UCLK4845:5540:60124006055:4560:4030Power Consumption78910MCLK = 25 MHzUCLK disabledMCLK = 25 MHz , DSPSubsystem clock = 60MHzCPU SubsystemDSP Subsystem0.840.51.0mAmAmA per MHzmA per MIPCPU Subsystem STANDBYDSP Subsystem STOPCPU Subsystem STANDBYDSP Subsystem IDLECPU Subsystem RUNDSP Subsystem STOPCPU Subsystem STANDBYDSP Subsystem ACTIVE†Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.‡Typical figures are at 25°C with nominal VDD + VIO and are for design aid only.
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